A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2003-January, Issue , 2003, Pages 29-40

  Mukherjee, S S ^a   Weaver, C ^a,b   Emer, J ^a   Reinhardt, S K ^a,b   Austin, T ^b  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Circuit faults; Circuit simulation; Computational modeling; Computer aided instruction; Costs; Error analysis; Fault diagnosis; Instruments; Microprocessors; Prefetching

Indexed keywords

CIRCUIT SIMULATION; COMPUTER AIDED ANALYSIS; COMPUTER AIDED DIAGNOSIS; COMPUTER AIDED INSTRUCTION; COMPUTER ARCHITECTURE; COSTS; ELECTRIC NETWORK ANALYSIS; ERROR ANALYSIS; ERRORS; FAILURE ANALYSIS; FAULT DETECTION; INSTRUMENTS; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; RADIATION HARDENING;

ARCHITECTURAL VULNERABILITY FACTOR; CIRCUIT FAULTS; COMPUTATIONAL MODEL; HIGH-PERFORMANCE MICROPROCESSORS; MICROARCHITECTURAL STATE; MICROPROCESSOR DESIGNS; PREFETCHING; SYSTEMATIC METHODOLOGY;

COST BENEFIT ANALYSIS;

EID: 84944403418     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2003.1253181     Document Type: Conference Paper

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