Multi-cell upset probabilities of 45nm high-k + metal gate SRAM devices in terrestrial and space environments

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2008, Pages 181-186

  Seifert, N ^a   Gill, B ^a   Foley, K ^a   Relangi, P ^b  

^a INTEL CORPORATION   (United States)

^b Stanford University   (United States)

Author keywords

MBU; MCU; Multi bit; Multi cell; Radiation; SER; SEU; Single bit; Single event; Soft error; Space; Terrestrial

Indexed keywords

AMPLIFICATION; COMMUNICATION SATELLITES; COMPUTER NETWORKS; DATA STORAGE EQUIPMENT; ERROR CORRECTION; HEAVY IONS; KETONES; LEARNING SYSTEMS; MAGNESIUM PRINTING PLATES; MICROPROCESSOR CHIPS; OFFSHORE OIL WELL PRODUCTION; ORBITS; RELIABILITY; STATIC RANDOM ACCESS STORAGE;

MBU; MCU; MULTI-BIT; MULTI-CELL; RADIATION; SER; SEU; SINGLE BIT; SINGLE EVENT; SOFT ERROR; SPACE; TERRESTRIAL;

ERROR ANALYSIS;

EID: 51549107392     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2008.4558882     Document Type: Conference Paper

References (22)

1. R.C. Baumann, "Radiation-induced soft errors in advanced semiconductor technologies", IEEE Transactions on Device and Materials Reliability, Volume 5, Issue 3, pp. 305 - 316, 2005
2. J.F. Ziegler, "Terrestrial cosmic rays", IBM Journal of Research and Development, volume 40, Nr. 1, 996, pp. 19-39
3. H.T. Nguyen et al., "Chip-level soft error estimation method", IEEE Transactions on Device and Materials Reliability, Volume 5, Issue 3, pp. 365 - 381, 2005
4. S.V. Walstra and Changhong Dai, "Circuit-level modeling of soft errors in integrated circuits", IEEE Transactions on Device and Materials Reliability, Volume 5, Issue 3, pp. 358-364, 2005
5. G. Hubert et al., "Prediction of Transient Induced by Neutron/Proton in CMOS combinational logic cells", IEEE International On-Line Testing Symposium (IOLTS), 2006.
6. F. Wrobel et al., " Incidence of multi-particle events on soft error rates caused by n-Si nuclear reactions," IEEE Trans. Nucl. Sci., vol. 47, pp. 2580 - 2585, 2000
7. G. C. Messenger, M.S. Ash, "Single Event Phenomena", Chapman & Hall (New York 1997).
8. JEDEC Standard JESD89A, "Measurement and Reporting of Alpha Particles and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices, October 2006.
9. E.L. Petersen et al., "Rate Prediction for Single Event Effects - a Critique", IEEE Trans. On Nuclear Science, Vol. 39, No.6, pp1577- 1599, 1992.
10. Jose Maiz et al., "Characterization of multi-cell soft error events in advanced SRAMs", Technical Digest of the IEEE International Electron Device Meeting, pp. 21.4.1-21.4.4, 2003
11. Norbert Seifert et al, "Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices", Proceedings of the IEEE International Physics Symposium, pp. 217-225, 2006
12. Eishi Ibe et al., "Spreading Diversity in Multi-cell Neutron-Induced Upsets with Device Scaling", Proceedings of Custom Integrated Circuits, pp. 437-444, 2006
13. Daniele Radaelli et al., "Investigation of Multi-Bit Upsets in a 150nm Technology SRAM Device", IEEE Transactions on Nucl. Science, Vol. 52, No.6, 2006.
14. Franz X. Ruckerbauer, Georg Georgakos, "Soft Error Rates in 65nm SRAMs - Analysis of new Phenomena", Proceedings of the IEEE International On-Line Testing Symposium, pp. 203-204, 2007
15. H. Quinn et al, "Static Proton and Heavy Ion Testing of the Xilinx Virtex-5 Device", To appear in the Proceedings of the IEEE Nuclear and Space Radiation Effects Conference Data Workshop, 2007, pp. 177-184.
16. T. Heijmen, P. Ngan, "Radiation-induced soft errors", presentation given at the 12th Annual Automotive Electronics Reliability Workshop (Nashville, Tennessee in May 2007) the authors report of a 30% MBU rate 65nm SRAMs
17. H. Yamaguchi et al., "Novel Mechanism of Neutron-Induced Multi-Cell Error in CMOS Devices Tracked Down from 3D Device Simulations", Simulation of Semiconductor Processes and Devices (SISPAD), pp. 184 - 187, 2006
18. K. Mistry, et al., "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging", Technical Digest of the IEEE International Electron Devices Meeting, pp. 247-250, 2007
19. P. Jain, J. Vasi, R.K. Lal, "SEU reliability analysis of advanced deep-submicron transistors", IEEE Transactions Device and Materials Reliability, Volume 5, Issue 2, pp.289 - 295, 2005
20. D.M. Hiemstra and A. Baril, "Single event upset characterization of the Pentium(R) MMX and Pentium(R) II microprocessors using proton irradiation", IEEE Trans. on Nucl. Science, Vol. 46, No.6, pp. 1453-1460, 1999.
21. Norbert Seifert et al., "On the Scalability of Redundancy based SER Mitigation Schemes", Proceedings of IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), pp. 1-9, 2007.
22. Creme96 code: https://creme96.nrl.navy.com; Crème stands for Cosmic Ray Effects on Micro Electronics