Fundamental limits of silicon

Proceedings of the IEEE

Volumn 89, Issue 3, 2001, Pages 227-239

  Keyes, Robert W ^a  

^a IBM RESEARCH   (United States)

Author keywords

Electronic devices; Integrated circuits; Scaling; Silicon technology; Wiring

Indexed keywords

EID: 0000171304     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.915372     Document Type: Article

References (50)

1. C. E. Shannon and W. Weaver, The Mathematical Theory of Communication. Urbana, IL: Univ. Illinois, 1949.
2. R. Landauer, "Minimal energy requirements in communication," Science, vol. 272, pp. 1914-1918, 1996.
3. _, "Uncertainty principle and minimal energy dissipation in the computer," Int. J. Theor. Phys., vol. 21, pp. 283-296, 1982.
4. C. H. Bennett, "Logical reversibility of computation," IBM J. Res. Dev., vol. 17, pp. 525-532, 1973.
5. C. H. Bennett and R. Landauer, "The fundamental physical limits of computation," Sci. Amer., vol. 253, no. 1, pp. 48-56, 1956.
6. R. Landauer, "Irreversibility and heat generation in the computing process," IBM J. Res. Dev., vol. 5, pp. 183-191, 1985.
7. K.-U. Stein, "Noise-induced error rate as limiting factor for energy per operation in digital IC's," IEEE J. Solid-State Circuits, vol. SC-12, pp. 527-530, 1977.
8. R. W. Keyes, "Physical problems and limits in computer logic," IEEE Spectr., vol. 6, pp. 36-45, May 1969.
9. D. B. Tuckerman and R. F. W. Pease, "High-performance heat sinking for VLSI," IEEE Electron Device Lett., vol. EDL-2, pp. 126-129, 1981.
10. R. W. Keyes, "Heat transfer in forced convection through fins," IEEE Trans. Electron Devices, vol. ED-31, pp. 1218-1221, 1984.
11. _, "Physical limits in digital electronics," Proc. IEEE, vol. 63, pp. 740-767, 1975.
12. [121 J. D. Meindl, "Low power microelectronics: Retrospect and prospect," Proc. IEEE, vol. 83, pp. 619-635, 1995.
13. [131 R. Landauer, "Wanted: A physically possible theory of physics," IEEE Spectr., vol. 4, pp. 105-109, Sept. 1987.
14. _, "Information is physical," Phys. Today, vol. 44, no. 5, p. 23, May 1991.
15. "Dig more coal - the PCs are coming," Forbes, pp. 70-72, May 1999.
16. G. E. Moore, "Progress in digital electronics," in IEDM Tech. Dig., 1975, pp. 11-13.
17. R. W. Keyes, private communication, 1998.
18. B. Hoeneisen and C. A. Mead, "Limitations iu microelectronics," Solid State Electron., vol. 15, pp. 819-987, 1972.
19. R. H. Dennard et al., "Design of ion-implanted MOSFETs with very small physical dimensions," IEEE J. Solid-State Circuits, vol SC-9, pp. 256-261, 1974.
20. P. K. Chatterjee et al., "The impact of scaling laws for MOS VLSI," IEEE Electron Device Lett., vol. EDL-1, pp. 220-223, 1980.
21. D. S. Gardner, J. D. Meindl, and K. C. Saraswat, "Interconnection and electremigration scaling theory," IEEE Trans. Electron Devices, vol. ED-34, p. 633, 1987.
22. R. W. Keyes, "Physical limits in information processing," in Advances in Electronics and Electron Physics. San Diego, CA: Academic, 1988, vol. 70, pp. 159-214.
23. Y. Taur et al., "CMOS scaling into the nanometer regime," Proc. IEEE, vol. 85, pp. 486-503, 1997.
24. W. Shockley, "Problems related to p-n junctions in silicon," Solid State Electron., vol. 2, pp. 35-67, 1961.
25. 2 interface," Bell Syst. Tech. J., vol. 46, pp. 1055-1133, 1967.
26. R. W. Keyes, "The effect of randomness in the distribution of impurity atoms on FET thresholds," Appl. Phys., vol. 8, pp. 251-259, 1975.
27. T. Mizuno et al., "Performance fluctuations of 0.10 μm MOSFETs," in Symp. VLSI Technol. Dig. Tech. Papers, 1994 , pp. 13-14.
28. D. Burnett et al., "Implications of fundamental threshold variations for high-density SRAM," in Symp. VLSI Technol. Dig. Tech. Papers, 1994, pp. 14-15.
29. J. F. Ziegler and G. R. Srinivasan, Eds., "Terrrestrial cosmic rays and soft errors," in IBM J. Res. Dev., 1996, vol. 40, no. 1, pp. 1-28.
30. L. B. Freeman, "Critical charge calculations for a bipolar SRAM array," IBM J. Res. Dev., vol. 40, pp. 119-129, 1996.
31. R. N. Noyce, "Large scale integration: What is yet to come?," Science, vol. 195, pp. 1102-1106, 1977.
32. Semiconductor Industry Association, "International technology map for semiconductors: 1998 update," International SEMATECH, Austin, TX.
33. R. R. Tummala, E. J. Rymaszewski, and A. Klopfenstein, Eds., Microelectronics Packaging Handbook. London, U.K.: Chapman & Hall, 1997.
34. R. J. Beall, "Packaging for a supercomputer," INTERCONf Tech. Paper, 18/3, 1974.
35. A. J. Blodgett, "Microelectronic packaging," Sci. Amer., vol. 121, no. 1, pp. 86-96, July 1983.
36. [361 D. M. Carlson, et al., "The ETA 10 liquid-nitrogen-cooled supercomputer," IEEE Trans. Electron Devices, vol. 36, pp. 1404-1413, 1989.
37. T. Watanabe, "Architecture of supercomputers - XEC supercomputer SX system," NEC Res. Dev., no. 73, pp. 1-6, 1984.
38. R. W. Keyes, "The wire-limited logic chip," IEEE J. Solid-State Circuits, vol. SC-17, pp. 1232-1233, 1982.
39. _, "Device limitations," in Materials Research Soc. Symp., Proc., Electron. Packaging Materials Science HI. vol. 108, 1988, pp. 5-12.
40. C. \V. Ho et al., "The thin-film module as a high-performance semiconductor package," IBM J. Res. Dev., vol. 26, pp. 286-296, 1982.
41. R. W. Keyes, "The power of connections," IEEE Circuits Devices Mag., vol. 7, no. 3, pp. 32-35, 1991.
42. _, The Physics of VLSI Systems. Reading, MA: AdJison-Wesley, 1987, pp. 178-182.
43. [431 W. E. Donath, "Wire length distribution for placements of computer logic," IBM J. Res. Dev., vol. 25, pp. 152-155, 1981.
44. J. A. Davis, V. K. De, and I. D. Meindl, "A stochastic wire-length distribution for gigascale integration," IEEE Trans. Electron Devices, vol. 45, pp. 580-597, 1998.
45. P. B. Ghate, "Electromigration-induced failures in interconnects," in Proc. Int. Reliability Physics, 1982, pp. 292-299.
46. Y. Nishi, "Challenges in CMOS technology," Solid State Technol., vol. 31, no. 11, pp. 115-119, Nov. 1988.
47. W. R. Heller, W. F. Mikhail, and W. E. Donath, "Prediction of wiring space requirements for LSI," in Proc. 14th Design Automat. Conf., New Orleans, LA, 1977, pp. 32-43.
48. P. C. Magnusson, Transmission Lines and Wave Propagation. Boston, MA: Allyn & Bacon, 1965, pp. 118-130.
49. F. H. Gaensslen, V. L. Rideout, E. J. Walker, and J. J. Walker, "Very small MOSFETs for low-temperature operation," IEEE Trans. Electron Devices, vol. ED-24, p. 218, 1977.
50. E. E. Davidson, B. D. McCredie, and W. V. Vilkelis, "Long lossy lines and their impact upon chip performance," IEEE Trans. Comp., Packag., Manufact. Technol. A, vol. 20, pp. 361-374, 1997.