Sub-60-nm quasi-planar FinFETs fabricated using a simplified process

IEEE Electron Device Letters

Volumn 22, Issue 10, 2001, Pages 487-489

  Lindert, Nick ^b   Chang, Leland ^b   Choi, Yang Kyu ^b   Anderson, Erik H ^c   Lee, Wen Chin ^d   King, Tsu Jae ^a,b   Bokor, Jeffrey ^b   Hu, Chenming ^a,b  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

^c LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

^d INTEL CORPORATION   (United States)

Author keywords

Double gate; Double resist process; Fin; FinFET; MOSFET; Short channel effects; SiGe gate

Indexed keywords

CAPACITANCE; CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; SCANNING ELECTRON MICROSCOPY;

SHORT CHANNEL EFFECTS;

MOSFET DEVICES;

EID: 0035475617     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.954920     Document Type: Article

References (10)

1. Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFETs at the 25 nm channel length generation
2. MOSFET scaling into the 10 nm regime
3. Gate length scaling and threshold voltage control of double-gate MOSFETs
4. A folded-channel MOSFET for deep-sub-tenth micron era
5. Sub 50-nm FinFET: PMOS
6. Calixarene G-line double resist process with 15nm resolution and large area exposure capability
7. An analytical solution to a double-gate MOSFET with undoped body
8. A computationally efficient model for inversion layer quantization effects in deep submicron n-channel MOSFETs
9. Ultrathin-body SOI MOSFET for deep-sub-tenth micron era
10. 30 nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D