Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 441-444

  Ieong, Meikei ^a   Jones, Erin C ^a   Kanarsky, Thomas ^a   Ren, Zhibin ^a   Dokumaci, Omer ^a   Roy, Ronnen A ^a   Shi, Leathen ^a   Furukawa, Toshiharu ^a   Taur, Yuan ^a   Miller, Robert J ^a   Wong, H S Philip ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BAND STRUCTURE; CARRIER MOBILITY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRON TRANSPORT PROPERTIES; GATES (TRANSISTOR); MATHEMATICAL MODELS; THRESHOLD VOLTAGE;

CARRIER TRANSPORT; DOUBLE GATE DEVICES; SHORT CHANNEL EFFECT CONTROL;

MOSFET DEVICES;

EID: 0035714565     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)