15nm gate length planar CMOS transistor

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 937-939

  Yu, Bin ^a   Wang, Haihong ^a   Joshi, Amol ^a   Xiang, Qi ^a   Ibok, Effiong ^a   Lin, Ming Ren ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); LEAKAGE CURRENTS; NITRIDES; OXIDATION; PERMITTIVITY; PHOTOLITHOGRAPHY; POLYSILICON; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE;

CMOS TRANSISTOR; ENERGY DELAY PRODUCTS; GATE DELAYS; GATE LENGTH;

MOSFET DEVICES;

EID: 0035714872     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)