Sub 50-nm FinFET: PMOS

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1999, Pages 67-70

  Huang, Xuejue ^a   Lee, Wen Chin ^a   Kuo, Charles ^a   Hisamoto, Digh ^a   Chang, Leland ^a   Kedzierski, Jakub ^a   Anderson, Erik ^a   Takeuchi, Hideki ^a   Choi, Yang Kyu ^a   Asano, Kazuya ^a   Subramanian, Vivek ^a   King, Tsu Jae ^a   Bokor, Jeffrey ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; TRANSMISSION ELECTRON MICROSCOPY;

FIN FIELD EFFECT TRANSISTOR; SELF ALIGNED DOUBLE GATE MOSFET; SHORT CHANNEL EFFECT;

MOSFET DEVICES;

EID: 0033329310     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)