The ballistic FET: Design, capacitance and speed limit

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 95-98

  Solomon, Paul M ^a   Laux, Steven E ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); MONTE CARLO METHODS; SEMICONDUCTING INDIUM GALLIUM ARSENIDE; SEMICONDUCTOR DEVICE STRUCTURES;

BALLISTIC FIELD EFFECT TRANSISTORS; INDIUM ALUMINUM ARSENIDE; SOFTWARE PACKAGE DAMOCLES;

FIELD EFFECT TRANSISTORS;

EID: 0035717885     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. The ballistic nanotransitor
2. On the performance limits
3. The ballistic nanotransistor: A simulation study
4. Ultra-short 25nm lattice matched InAlAs/InGaAs HEMTS within the range of 400GHz cutoff frequency
5. Ballistic metal-oxide-semiconductor field effect transistor
6. Physics at the limit of VLSI scaling
7. On experimental determination of carrier velocity in deeply scaled NMOS: How close to the thermal limit?