Device scaling limits of Si MOSFETs and their application dependencies

Proceedings of the IEEE

Volumn 89, Issue 3, 2001, Pages 259-287

  Frank, David J ^a   Dennard, Robert H ^a   Nowak, Edward ^a   Solomon, Paul M ^a   Taur, Yuan ^a   Wong, Hon Sum Philip ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

CMOS; Device design; Discrete dopants; Double gate mosfet; DRAM; High k dielectrics; High performance logic; Leakage currents; Limits; Low power; MOSFET; Nanotechnology; Power density; Scale length; Scaling; SRAM; Tunneling

Indexed keywords

EID: 33646900503     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.915374     Document Type: Article

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