High performance of planar double gate MOSFETs with thin backgate dielectrics

Annual Device Research Conference Digest

Volumn , Issue , 2001, Pages 28-29

  Jones, E C ^a   Ieong, M ^a   Kanarsky, T ^a   Dokumaci, O ^a   Roy, R A ^a   Shi, L ^a   Furukawa, T ^a   Miller, R J ^a   Wong, H S P ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; POLYSILICON; SILICON ON INSULATOR TECHNOLOGY;

SHORT-CHANNEL EFFECTS (SCE); THIN BACKGATE DIELECTRICS;

MOSFET DEVICES;

EID: 0034875418     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)