High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 437-440

  Kedzierski, Jakub ^a   Fried, David M ^a   Nowak, Edward J ^a   Kanarsky, Thomas ^a   Rankin, Jed H ^a   Hanafi, Hussein ^a   Natzle, W ^a   Boyd, Diane ^a   Zhang, Ying ^a   Roy, Ronnen A ^a   Newbury, J ^a   Yu, Chienfan ^a   Yang, Qingyun ^a   Saunders, P ^a   Willets, Christa P ^a   Johnson, A ^a   Cole, S P ^a   Young, H E ^a   Carpenter, N ^a   Rakowski, D ^a   Rainey, Beth Ann ^a   Cottrell, Peter E ^a   Ieong, Meikei ^a   Wong, H S Philip ^a   more..

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; OPTIMIZATION; POLYSILICON; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; TRANSMISSION ELECTRON MICROSCOPY;

ASYMMETRIC GATE DEVICES; DRAIN CURRENTS; POLYSILICON GATES; SYMMETRIC GATE DEVICES;

FIELD EFFECT TRANSISTORS;

EID: 0035714369     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)