30nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 45-48

  Chau, R ^a   Kavalieros, J ^a   Roberds, B ^a   Schenker, R ^a   Lionberger, D ^a   Barlage, D ^a   Doyle, B ^a   Arghavani, R ^a   Murthy, A ^a   Dewey, G ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRODES; MOSFET DEVICES; POLYSILICON; SEMICONDUCTOR DEVICE MANUFACTURE;

POLYSILICON GATE ELECTRODES;

CMOS INTEGRATED CIRCUITS;

EID: 0003899569     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)