200 mm process integration for a 0.15 μm channel-length CMOS technology using mixed X-ray/optical lithography

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1994, Pages 695-698

  Subbanna, S ^a   Ganin, E ^a   Crabbe, E ^a   Comfort, J ^a   Wu, S ^a   Agnello, P ^a   Martin, B ^a   McCord, M ^a   Ng, H ^a   Newman, T ^a   McFarland, P ^a   Sun, J ^a   Snare, J ^a   Acovic, A ^a   Ray, A ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC PROPERTIES; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT MANUFACTURE; RANDOM ACCESS STORAGE; SILICON ON INSULATOR TECHNOLOGY; VOLTAGE CONTROL; X RAY LITHOGRAPHY;

GATE LEVEL LITHOGRAPHY; SHALLOW TRENCH ISOLATION;

CMOS INTEGRATED CIRCUITS;

EID: 0028744092     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)