Gate Oxide Scaling Limits and Projection

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 319-322

  Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE TRAPPING; MOSFET DEVICES; DEFECTS; ELECTRIC BREAKDOWN; ELECTRON TUNNELING; GATES (TRANSISTOR); OXIDES; SEMICONDUCTOR PLASMAS;

GATE DEPLETION; GATE OXIDE; MOBILITY DEGRADATION; MOSFETS; OXIDE SCALING; PLASMA PROCESS; POLY GATES; SCALING LIMITS; TIME DEPENDENT; TUNNELING LEAKAGE;

GATES (TRANSISTOR); MOSFET DEVICES;

GATE OXIDE SCALING LIMITS; MOBILITY DEGRADATION; PLASMA PROCESS DAMAGE; TUNNELING LEAKAGE;

EID: 0030387118     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.553593     Document Type: Conference Paper

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