HI-CMOS III TECHNOLOGY.

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1984, Pages 59-62

  Meguro, S ^a   Ikeda, S ^a   Nagasawa, K ^a   Koike, A ^a   Yasui, T ^a   Sakai, Y ^a   Hayashida, T ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS;

BURIED CHANNEL LDD (BCLDD) PMOS; HI-CMOS III TECHNOLOGY; LIGHTLY DOPED DRAIN (LDD) NMOS; POST-CONTACT-DOPING; SHORT CHANNEL EFFECT REDUCTION;

SEMICONDUCTOR DEVICES, MOS;

BURIED CHANNEL LDD (BCLDD) PMOS; HI-CMOS III TECHNOLOGY; LIGHTLY DOPED DRAIN (LDD) NMOS; POST-CONTACT-DOPING; SHORT CHANNEL EFFECT REDUCTION;

EID: 0021640146     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iedm.1984.190641     Document Type: Conference Paper

References (2)