Scaled 1.8V, 0.18μm gate length CMOS technology: device design and reliability considerations

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1995, Pages 415-418

  Rodder, M ^a   Aur, S ^a   Chen, I C ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; DEPOSITION; ETCHING; GATES (TRANSISTOR); MOS DEVICES; PERFORMANCE; SEMICONDUCTOR DOPING; TRANSISTORS;

HIGH CARRIER VELOCITY; HIGHLY DOPE DRAIN EXTENSION; SUPERSTEEP RETROGRADE;

CMOS INTEGRATED CIRCUITS;

EID: 0029521766     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)