A High Performance 0.25 pm Logic Technology Optimized for 1.8V Operation

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 847-850

  Bohr, M ^a   Ahmed, S S ^a   Ahmed, S U ^a   Bost, M ^a   Ghani, T ^a   Greason, J ^a   Hainsey, R ^a   Jan, C ^a   Packan, P ^a   Sivakumar, S ^a   Thompson, S ^a   Tsai, J ^a   Yang, S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); LITHOGRAPHY; MOSFET DEVICES; OPTIMIZATION; RANDOM ACCESS STORAGE; SEMICONDUCTOR DOPING; SEMICONDUCTOR STORAGE; SILICON NITRIDE; TITANIUM COMPOUNDS; TRANSCONDUCTANCE;

CELL-SIZE; HIGH ASPECT RATIO; LOGIC TECHNOLOGY; LOW POWER; METAL LINE; PERFORMANCE; PLANARIZATION;

ASPECT RATIO; INTEGRATED CIRCUIT MANUFACTURE;

LOGIC TECHNOLOGY; PLANARIZATION; SHALLOW TRENCH ISOLATION; SURFACE CHANNEL EFFECT;

EID: 0030383519     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.554112     Document Type: Conference Paper

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