Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 113-116

  Wann, Clement ^a   Assaderaghi, Fariborz ^a   Dennard, Robert ^a   Hu, Chenming ^b   Shahidi, Ghavam ^a   Taur, Yuan ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC RESISTANCE; ELECTRIC VARIABLES MEASUREMENT; GATES (TRANSISTOR); LEAKAGE CURRENTS; LOGIC CIRCUITS; OPTIMIZATION; PERFORMANCE; SEMICONDUCTOR DOPING; SOLID STATE OSCILLATORS; WAVEFORM ANALYSIS;

DYNAMIC THRESHOLD MOSFET; HIGH SPEED PULSE MEASUREMENT; RC DELAY; RING OSCILLATOR;

MOSFET DEVICES;

EID: 0030403888     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.553134     Document Type: Conference Paper

References (4)

1. Y. Mii, Y. Taur, Y. Lee, D. Klaus, and J. Bucchignano, "An ultra-low power 0.1 CMOS," 1994 Symposium on VLSI Technology Digest ofTechnical Papers.
2. M. Shin'ichiro, D. Takakuni, M. Yasuyuki, A. Takahiro, S. Satoshi, and Y. Junzo, "1-V power supply high-speed digital circuits technology with multithreshold-voltage CMOS," IEEE Journal of Solid-state Circuits, VOL. 30, NO. 8, Aug. 1995, pp. 847-54.
3. J. Gautier, K. Jenkins, and J. Sun, "Body charge related transient effects in floating body SOI NMOSFETs," International Electron Devices Meeting Technical Digest, 1995, pp. 623¬ 626.
4. F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. Ko, and C. Hu, "A dynamic-threshold MOSFET for ultra-low voltage operation," International Electron Devices Meeting Technical Digest, 1994, pp. 809-12.