0.18um Dual Vt MOSFET Process and Energy-Delay Measurement

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 851-854

  Chen, Zongjian ^a   Diaz, Carlos ^b   Plummer, James D ^a   Cao, Min ^b   Greene, Wayne ^b  

^a Stanford University   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL STORAGE; POWER CONTROL; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC VARIABLES MEASUREMENT; INTEGRATED CIRCUIT MANUFACTURE;

CHANNEL LENGTH; CURRENT DRIVES; DELAY MEASUREMENTS; DEVICE DATA; DUAL-VT; ENERGY DELAY; ENERGY DELAY PRODUCT; MOSFET PROCESS; POWER-CONTROL; PROCESS DELAY;

THRESHOLD VOLTAGE; MOSFET DEVICES;

ENERGY DELAY PRODUCT MEASUREMENT; IDLING FACTOR; THRESHOLD VOLTAGES;

EID: 0030387081     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.554113     Document Type: Conference Paper

References (6)

1. Liu, D., et al. “Trading Speed for Low Power by Choice of Supply and Threshold Voltage,” IEEE Joum. of Solid State Circuits, Vol. 28, No.1, p.10-17, Jan., 1993.
2. J. Burr, J. Shott, “A 200mV Self Testing Encoder/Decoder Using Stanford Ultra-Low-Power CMOS,” ISSCC Digest of Technical Papers, pp.84-5, Feb., 1994.
3. Z. Chen, J. Plummer, “CMOS Technology Scaling for Low Voltage Low Power Applications”, 1994 IEEE Symposium on Low Power Electronics, p56-58.
4. . Nandakumar, M. et al. “0.25um gate length CMOS technology for 1V low power applications - device design and power / performance considerations” 1996 Symposium on VLSI technology Digest of Technical papers, p 68
5. . Mii, Y./et al. “An ultra-low power O.lum CMOS” Proceedings of 1994 VLSI Technology Symposium,p9-10.
6. .Horowitz, M. et al. “Low power digital design” Proceedings of 1994 IEEE Symposiumon Low Power Electronics. p8