High performance 0.35 μm logic technology for 3.3 V and 2.5 V operation

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1994, Pages 273-276

  Bohr, M ^a   Ahmed, S U ^a   Brigham, L ^a   Chau, R ^a   Gasser, R ^a   Green, R ^a   Hargrove, W ^a   Lee, E ^a   Natter, R ^a   Thompson, S ^a   Weldon, K ^a   Yang, S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL CAPACITY; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LITHOGRAPHY; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; VOLTAGE CONTROL;

BIPOLAR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR; LATERAL ISOLATION ENCROACHMENT; PLANARIZED INTERCONNECT; SHALLOW TRENCH ISOLATION; STATIC RANDOM ACCESS MEMORY;

LOGIC CIRCUITS;

EID: 0028754969     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (41)