Suppression of Delay Tinie Instability on Frequency using Field Shield Isolation Technology for Deep Sub-Micron SOI Circuits

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 129-132

  Maeda, S ^a   Yamaguchi, Y ^a   Kim, I J ^a   Iwamatsu, T ^a   Ipposhi, T ^a   Miyamoto, S ^a   Maegawa, S ^a   Ueda, K ^b   Nii, K ^b   Mashiko, K ^a   Inoue, Y ^a   Miyoshi, H ^a  

^a ULSI Laboratory   (Japan)

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; ELECTRIC RESISTANCE; ELECTRODES; FREQUENCIES; GATES (TRANSISTOR); MOSFET DEVICES; OXIDES; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; SIMULATION;

AREA PENALTY; BODY POTENTIAL; BODY RESISTANCE; DEEP SUB-MICRON; DEEP-SUB MICRONS; DELAY TIME; GATE ARRAYS; ISOLATION TECHNOLOGY; OPERATING FREQUENCY; SOI CIRCUITS;

TIMING CIRCUITS; ELECTRIC SHIELDING;

FIELD SHIELD ISOLATION TECHNOLOGY; LOCOS ISOLATION; SIMOX WAFERS;

EID: 0030393799     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.553138     Document Type: Conference Paper

References (3)

1. D. Suh, et al., IEEE Trans, on Electron Devices, vol ED-42, p.728, (1995)
2. T. Iwamatsu, et al., I E E E Trans, on Electron Devices, vol ED-42, p.1934, (1995)
3. I.-J. Kim, et al., in Proc. ECS Spring Meeting, vol. 96-1, p.548 or vol. 96-3, p.397, (1996)