Back-gate forward bias method for low-voltage CMOS digital circuits

IEEE Transactions on Electron Devices

Volumn 43, Issue 6, 1996, Pages 904-910

  Chen, Ming Jer ^a   Ho, Jib Shin ^a   Huang, Tzuen Hsi ^a   Yang, Chuang Hen ^a   Jou, Yeh Ning ^b   Terry, Wu ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b Electronics Res and Serv Org/TTRI   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; DIGITAL CIRCUITS; ELECTRIC INVERTERS; ELECTRIC VARIABLES MEASUREMENT; INTEGRATED CIRCUIT MANUFACTURE; LINEAR INTEGRATED CIRCUITS; MOSFET DEVICES;

DRAIN CURRENT; GATE FORWARD BIAS METHOD; GATE VOLTAGE; IMPACT IONIZATION; THRESHOLD VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0030164323     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.502122     Document Type: Article

References (11)

1. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, and J. Yamada, "1 V high-speed digital circuit technology with 0.5 /um multi-threshold CMOS," in Proc. IEEE Int. ASIC Conf. and Exhibit, Sept. 1993, pp. 186-189.
2. M. Horiguchi, T. Sakata, and K. Huh, "Swilched-suurce-impedance CMOS circuit for low standby subthreshold current giga scale LSI's," IEEE J. Solid-State Circuits, vol. 28, pp. 1131-1135, Nov. 1993.
3. T. Kawahara, M. Horiguchi, Y. Kawajiri, G. Kitsukawa, T. Kure, and M. Aoki. "Subthreshold current reduction for decoded-driver by self-reverse biasing," IEEE L Siilid-Stale Circ.uits. vol. 28, pp. 1136-1144, Nov. 1993.
4. J. B. Burr and J. Shott. "A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOS," in IEEE Int. Salid-State. C.ircuil Conf.. Dig. Tech. Papers, Feb. 1994, pp. 84-85.
5. F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and C. Hu, "A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation," in IEEE Int. Electron Devices Mtg., 'lech. Dig., Dec. 1994. pp. 809-812.
6. T. Andoh, A. Furukawa, and T. Kunio, "Design methodology for lowvoltage MOSFET's," in IEEE Im. Electron Devices Mtg.. Tech. Dig., Dec. 1994, pp. 79-84.
7. T. H. Huang and M. J. Chen, "Empirical modeling for gate-controlled collector current of lateral bipolar transistors in an n-MOSFET structure," Solid-State Electronics, vol. 38, pp. 115-119, Jan. 1995.
8. [81 J. S. Ho, T. H. Huang, and M. J. Chen, "High gain p-n-p gated lateral bipolar action in a fully depleted counter-type channel p-MOSFF.T structure," Solid-State Electron., vol. 39, pp. 261-267, Feb. 1996.
9. C. Hu, "Low-voltage CMOS device scaling," in IEEE Int. Solid-Slate Circuit ConJ. Dig. Tech. Papers, Feb 1994, pp. 86-87.
10. T. H. Huang and M. J. Chen, "Base current reversal phenomenon in a CMOS compatible high gain n-p-n gated lateral bipolar transistor," IEEE Trans. Electron Devices, vol. 42, pp. 321-327, Feb. 1995.
11. M. .1. Chen, J. S. Ho, and T. H. Huang, "Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling," IEEE J. Solid-State Circuits, vol. 31, pp. 259-262, Feb. 1996.