High performance MOSFET design with highly controllable gate length and low RC delay multilevel interconnects technology for high speed logic devices

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1995, Pages 705-708

  Oyamatsu, H ^a   Kasai, K ^a   Matsunaga, N ^a   Igarashi, H ^a   Yamaguchi, T ^a   Asamura, T ^a   Azuma, A ^a   Shibata, H ^a   Kinugawa, M ^a   Kakumu, M ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; ELECTRIC CURRENTS; GATES (TRANSISTOR); ION IMPLANTATION; LITHOGRAPHY; LSI CIRCUITS; PERFORMANCE; SEMICONDUCTOR DEVICE STRUCTURES; SILICON COMPOUNDS;

CHANNEL ISOLATION REGION; DELAY MULTILEVEL INTERCONNECTS; HIGH CURRENT DRIVABILITY; HIGH SPEED LOGIC DEVICES; HIGHLY CONTROLLABLE GATE LENGTH; PLANARIZATION PROCESS;

MOSFET DEVICES;

EID: 0029544649     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)