DOUBLE LAYER METAL CHMOS III TECHNOLOGY.

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1984, Pages 56-58

  Smith, R J ^a   Sery, G ^a   McCollum, J ^a   Orton, J ^a   Mantha, B ^a   Smudski, J ^a   Chi, T ^a   Smith, S ^a   Dishaw, J P ^a   Kokkonen, K ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS, MICROCOMPUTER; INTEGRATED CIRCUITS, VLSI; LOGIC DESIGN; TRANSISTORS - PERFORMANCE;

HIGH PERFORMANCE CMOS TECHNOLOGY (CMOSIII); INTEGRATED-CIRCUIT INTERCONNECTIONS; LIGHTLY DOPED DRAIN; RANDOM LOGIC;

SEMICONDUCTOR DEVICES, MOS;

EID: 17044457645     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)