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Volumn 10, Issue , 2010, Pages 1-144

Computer architecture performance evaluation methods

Author keywords

analytical modeling; architectural simulation; computer architecture; FPGA accelerated simulation; parallel simulation; performance evaluation; performance metrics; sampled simulation; statistical simulation; workload characterization

Indexed keywords

ACCELERATED SIMULATIONS; ANALYTICAL MODELING; ARCHITECTURAL SIMULATION; PARALLEL SIMULATIONS; STATISTICAL SIMULATION; WORKLOAD CHARACTERIZATION;

EID: 77954911192     PISSN: 19353235     EISSN: 19353243     Source Type: Book Series    
DOI: 10.2200/S00273ED1V01Y201006CAC010     Document Type: Conference Paper
Times cited : (43)

References (199)
  • 2
    • 33947715600 scopus 로고    scopus 로고
    • IPC considered harmful for multiprocessor workloads
    • DOI 10.1109/MM.2006.73
    • A. R. Alameldeen and D. A. Wood. IPC considered harmful for multiprocessor workloads. IEEE Micro, 26(4):8-17, July 2006. DOI: 10.1109/MM.2006.73 6 (Pubitemid 46504885)
    • (2006) IEEE Micro , vol.26 , Issue.4 , pp. 8-17
    • Alameldeen, A.R.1    Wood, D.A.2
  • 3
    • 0022806145 scopus 로고
    • Cache coherence protocols: Evaluation using a multiprocessor simulation model
    • DOI 10.1145/6513.6514
    • J. Archibald and J.-L. Baer. Cache coherence protocols: Evaluation using a multiprocessor simulation model. ACM Transactions on Computer Systems (TOCS), 4(4):273-298, November 1986. DOI: 10.1145/6513.6514 81 (Pubitemid 17476403)
    • (1986) ACM Transactions on Computer Systems , vol.4 , Issue.4 , pp. 273-298
    • Archibald, J.1    Baer, J.-L.2
  • 4
    • 70649102910 scopus 로고    scopus 로고
    • COTSon: Infrastructure for full system simulation
    • January DOI: 10.1145/1496909.1496921 58 97
    • E. Argollo, A. Falcón, P. Faraboschi, M. Monchiero, and D. Ortega. COTSon: Infrastructure for full system simulation. SIGOPS Operating System Review, 43(1):52-61, January 2009. DOI: 10.1145/1496909.1496921 58, 97
    • (2009) SIGOPS Operating System Review , vol.43 , Issue.1 , pp. 52-61
    • Argollo, E.1    Falcón, A.2    Faraboschi, P.3    Monchiero, M.4    Ortega, D.5
  • 5
    • 33745197022 scopus 로고    scopus 로고
    • RAMP: Research accelerator for multiple processors\a community vision for a shared experimental parallel HW/SW platform
    • University of California, Berkeley
    • Arvind, K. Asanovic, D. Chiou, J. C. Hoe, C. Kozyrakis, S.-L. Lu, M. Oskin, D. Patterson, J. Rabaey, and J. Wawrzynek. RAMP: Research accelerator for multiple processors\a community vision for a shared experimental parallel HW/SW platform. Technical report, University of California, Berkeley, 2005. 102
    • (2005) Technical Report , pp. 102
    • Asanovic, A.K.1    Chiou, D.2    Hoe, J.C.3    Kozyrakis, C.4    Lu, S.-L.5    Oskin, M.6    Patterson, D.7    Rabaey, J.8    Wawrzynek, J.9
  • 6
    • 36749086936 scopus 로고    scopus 로고
    • UNISIM: An open simulation environment and library for complex architecture design and collaborative development
    • DOI 10.1109/L-CA.2007.12
    • D. I. August, S. Girbal J. Chang, D. G. Pérez, G. Mouchard, D. A. Penry, O. Temam, and N Vachharajani. UNISIM:An open simulation environment and library for complex architecture design and collaborative development. IEEE Computer Architecture Letters, 6(2):45-48, February 2007. DOI: 10.1109/L-CA.2007.12 61 (Pubitemid 350214235)
    • (2007) IEEE Computer Architecture Letters , vol.6 , Issue.2
    • August, D.1    Chang, J.2    Girbal, S.3    Gracia-Perez, D.4    Mouchard, G.5    Penry, D.6    Temam, O.7    Vachharajani, N.8
  • 7
    • 0036469652 scopus 로고    scopus 로고
    • SimpleScalar: An infrastructure for computer system modeling
    • February 51, 55
    • T. Austin, E. Larson, and D. Ernst. SimpleScalar: An infrastructure for computer system modeling. IEEE Computer, 35(2):59-67, February 2002. 51, 55
    • (2002) IEEE Computer , vol.35 , Issue.2 , pp. 59-67
    • Austin, T.1    Larson, E.2    Ernst, D.3
  • 8
    • 33749079198 scopus 로고    scopus 로고
    • BioPerf: A benchmark suite to evaluate high-performance computer architecture on bioinformatics applications
    • DOI 10.1109/IISWC.2005.1526013, 1526013, Proceedings of the 2005 IEEE International Symposium on Workload Characterization, IISWC-2005
    • D. A. Bader, Y. Li, T. Li, and V. Sachdeva. BioPerf: A benchmark suite to evaluate high-performance computer architecture on bioinformatics applications. In Proceedings of the 2005 IEEE International Symposium on Workload Characterization (IISWC), pages 163-173, October 2005. DOI: 10.1109/IISWC.2005. 1526013 16 (Pubitemid 44460147)
    • (2005) Proceedings of the 2005 IEEE International Symposium on Workload Characterization, IISWC-2005 , vol.2005 , pp. 163-173
    • Bader, D.A.1    Li, Y.2    Li, T.3    Sachdeva, V.4
  • 11
    • 0032681099 scopus 로고    scopus 로고
    • An integrated functional performance simulator
    • May/June DOI: 10.1109/40.768499 55
    • C. Bechem, J. Combs, N. Utamaphetai, B. Black, R. D. Shawn Blanton, and J. P. Shen. An integrated functional performance simulator. IEEE Micro, 19(3):26-35, May/June 1999. DOI: 10.1109/40.768499 55
    • (1999) IEEE Micro , vol.19 , Issue.3 , pp. 26-35
    • Bechem, C.1    Combs, J.2    Utamaphetai, N.3    Black, B.4    Shawn Blanton, R.D.5    Shen., J.P.6
  • 16
    • 33846535493 scopus 로고    scopus 로고
    • The M5 simulator: Modeling networked systems
    • DOI 10.1109/MM.2006.82
    • N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Rein-hardt. The M5 simulator: Modeling networked systems. IEEE Micro, 26(4):52-60, 2006. DOI: 10.1109/MM.2006.82 54, 55, 61 (Pubitemid 46504889)
    • (2006) IEEE Micro , vol.26 , Issue.4 , pp. 52-60
    • Binkert, N.L.1    Dreslinski, R.G.2    Hsu, L.R.3    Lim, K.T.4    Saidi, A.G.5    Reinhardt, S.K.6
  • 24
    • 21244474546 scopus 로고    scopus 로고
    • Predicting inter-thread cache contention on a chip multi-processor architecture
    • Proceedings - 11th International Symposium on High-Performance Computer Architecture, HPCA-11 2005
    • D. Chandra, F. Guo, S. Kim, and Y. Solihin. Predicting inter-thread cache contention on a chip-multiprocessor architecture. In Proceedings of the Eleventh International Symposium on High Performance Computer Architecture (HPCA), pages 340-351, February 2005. 7, 91, 93 (Pubitemid 41731513)
    • (2005) Proceedings - International Symposium on High-Performance Computer Architecture , pp. 340-351
    • Chandra, D.1    Guo, F.2    Kim, S.3    Solihin, Y.4
  • 26
    • 77958075524 scopus 로고    scopus 로고
    • SlackSim: A platform for parallel simulation of CMPs on CMPs
    • 20-29 May DOI: 10.1145/1577129.1577134 97, 100
    • J. Chen, M. Annavaram, and M. Dubois. SlackSim: A platform for parallel simulation of CMPs on CMPs. ACM SIGARCH Computer Architecture News, 37(2):20-29, May 2009. DOI: 10.1145/1577129.1577134 97, 100
    • (2009) ACM SIGARCH Computer Architecture News , vol.37 , Issue.2
    • Chen, J.1    Annavaram, M.2    Dubois, M.3
  • 28
    • 4243073044 scopus 로고    scopus 로고
    • Parallel simulation of chip-multiprocessor architectures
    • July DOI: 10.1145/643114.643116 100
    • M. Chidester and A. George. Parallel simulation of chip-multiprocessor architectures. ACM Transactions on Modeling and Computer Simulation, 12(3):176-200, July 2002. DOI: 10.1145/643114.643116 100
    • (2002) ACM Transactions on Modeling and Computer Simulation , vol.12 , Issue.3 , pp. 176-200
    • Chidester, M.1    George, A.2
  • 29
    • 75449097194 scopus 로고    scopus 로고
    • Accurate functional-first multicore simulators
    • July DOI: 10.1109/L-CA.2009.44 57 102
    • D. Chiou, H. Angepat, N. A. Patil, and D. Sunwoo. Accurate functional-first multicore simulators. IEEE Computer Architecture Letters, 8(2):64-67, July 2009. DOI: 10.1109/L-CA.2009.44 57, 102
    • (2009) IEEE Computer Architecture Letters , vol.8 , Issue.2 , pp. 64-67
    • Chiou, D.1    Angepat, H.2    Patil, N.A.3    Sunwoo, D.4
  • 33
    • 0038008203 scopus 로고    scopus 로고
    • MisSPECulation: Partial and misleading use of SPEC CPU2000 in computer architecture conferences
    • June DOI: 10.1109/ISCA.2003.1206988, 17
    • D. Citron. MisSPECulation: Partial and misleading use of SPEC CPU2000 in computer architecture conferences. In Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA), pages 52-59, June 2003. DOI: 10.1109/ISCA.2003.1206988 17
    • (2003) Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA) , pp. 52-59
    • Citron, D.1
  • 35
    • 1842860791 scopus 로고    scopus 로고
    • Combining trace sampling with single pass methods for efficient cache simulation
    • June DOI: 10.1109/12.689650 54, 76
    • T. M. Conte, M. A. Hirsch, and W. W. Hwu. Combining trace sampling with single pass methods for efficient cache simulation. IEEE Transactions on Computers, 47(6):714-720, June 1998. DOI: 10.1109/12.689650 54, 76
    • (1998) IEEE Transactions on Computers , vol.47 , Issue.6 , pp. 714-720
    • Conte, T.M.1    Hirsch, M.A.2    Hwu, W.W.3
  • 42
    • 1842871850 scopus 로고
    • Profile-driven sampled trace generation
    • IBM Research Division, T. J. Watson Research Center April 70
    • P. K. Dubey and R. Nair. Profile-driven sampled trace generation. Technical Report RC 20041, IBM Research Division, T. J. Watson Research Center, April 1995. 70
    • (1995) Technical Report RC 20041
    • Dubey, P.K.1    Nair, R.2
  • 49
    • 25844526328 scopus 로고    scopus 로고
    • BLRL: Accurate and efficient warmup for sampled processor simulation
    • DOI 10.1093/comjnl/bxh103
    • L. Eeckhout, Y. Luo, K. De Bosschere, and L. K. John. BLRL: Accurate and efficient warmup for sampled processor simulation. The Computer Journal, 48(4):451-459, May 2005. DOI: 10.1093/comjnl/bxh103 75 (Pubitemid 41386602)
    • (2005) Computer Journal , vol.48 , Issue.4 , pp. 451-459
    • Eeckhout, L.1    Luo, Y.2    De Bosschere, K.3    John, L.K.4
  • 50
    • 0242577987 scopus 로고    scopus 로고
    • Statistical simulation: Adding efficiency to the computer designer's toolbox
    • Sept/Oct DOI: 10.1109/MM.2003.1240210, 81
    • L. Eeckhout, S. Nussbaum, J. E. Smith, and K. De Bosschere. Statistical simulation: Adding efficiency to the computer designer's toolbox. IEEE Micro, 23(5):26-38, Sept/Oct 2003. DOI: 10.1109/MM.2003.1240210 81
    • (2003) IEEE Micro , vol.23 , Issue.5 , pp. 26-38
    • Eeckhout, L.1    Nussbaum, S.2    Smith, J.E.3    De Bosschere, K.4
  • 51
    • 33749073811 scopus 로고    scopus 로고
    • Exploiting program microarchitecture independent characteristics and phase behavior for reduced benchmark suite simulation
    • DOI 10.1109/IISWC.2005.1525996, 1525996, Proceedings of the 2005 IEEE International Symposium on Workload Characterization, IISWC-2005
    • L. Eeckhout, J. Sampson, and B. Calder. Exploiting program microarchitecture independent characteristics and phase behavior for reduced benchmark suite simulation. In Proceedings of the 2005 IEEE International Symposium on Workload Characterization (IISWC), pages 2-12, October 2005. DOI: 10.1109/IISWC.2005.1525996 27, 70 (Pubitemid 44460130)
    • (2005) Proceedings of the 2005 IEEE International Symposium on Workload Characterization, IISWC-2005 , vol.2005 , pp. 2-12
    • Eeckhout, L.1    Sampson, J.2    Calder, B.3
  • 52
    • 0037325558 scopus 로고    scopus 로고
    • Designing workloads for computer architecture research
    • February 27
    • L. Eeckhout, H. Vandierendonck, and K. De Bosschere. Designing workloads for computer architecture research. IEEE Computer, 36(2):65-71, February 2003. 27
    • (2003) IEEE Computer , vol.36 , Issue.2 , pp. 65-71
    • Eeckhout, L.1    Vandierendonck, H.2    De Bosschere, K.3
  • 53
    • 1442333868 scopus 로고    scopus 로고
    • Quantifying the impact of input data sets on program behavior and its applications
    • February 18, 25
    • L. Eeckhout, H. Vandierendonck, and K. De Bosschere. Quantifying the impact of input data sets on program behavior and its applications. Journal of Instruction-Level Parallelism, 5, February 2003. http://www.jilp.org/vol5. 18, 25
    • (2003) Journal of Instruction-Level Parallelism , vol.5
    • Eeckhout, L.1    Vandierendonck, H.2    De Bosschere, K.3
  • 54
    • 33744483411 scopus 로고    scopus 로고
    • Enhancing multiprocessor architecture simulation speed using matched-pair comparison
    • DOI 10.1109/ISPASS.2005.1430562, 1430562, ISPASS 2005 - IEEE International Symposium on Performance Analysis of Systems and Software
    • M. Ekman and P. Stenström. Enhancing multiprocessor architecture simulation speed using matched-pair comparison. In Proceedings of the 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 89-99, March 2005. DOI: 10.1109/ISPASS.2005.1430562 70, 79 (Pubitemid 43804306)
    • (2005) ISPASS 2005 - IEEE International Symposium on Performance Analysis of Systems and Software , vol.2005 , pp. 89-99
    • Ekman, M.1    Stenstrom, P.2
  • 60
    • 0031140923 scopus 로고    scopus 로고
    • Understanding some simple processor-performance limits
    • May DOI: 10.1147/rd.413.0215 6
    • P. G. Emma. Understanding some simple processor-performance limits. IBM Journal of Research and Development, 41(3):215-232, May 1997. DOI: 10.1147/rd.413.0215 6
    • (1997) IBM Journal of Research and Development , vol.41 , Issue.3 , pp. 215-232
    • Emma, P.G.1
  • 61
    • 47249094055 scopus 로고    scopus 로고
    • System-level performance metrics for multi-program workloads
    • May/June DOI: 10.1109/MM.2008.44 8, 11
    • S. Eyerman and L. Eeckhout. System-level performance metrics for multi-program workloads. IEEE Micro, 28(3):42-53, May/June 2008. DOI: 10.1109/MM.2008.44 8, 11
    • (2008) IEEE Micro , vol.28 , Issue.3 , pp. 42-53
    • Eyerman, S.1    Eeckhout, L.2
  • 67
    • 0030712794 scopus 로고    scopus 로고
    • Modeling cost/performance of a parallel computer simulator
    • January DOI: 10.1145/244804.244808, 100
    • B. Falsafi and D. A. Wood. Modeling cost/performance of a parallel computer simulator. ACM Transactions on Modeling and Computer Simulation (TOMACS), 7(1):104-130, January 1997. DOI: 10.1145/244804.244808 100
    • (1997) ACM Transactions on Modeling and Computer Simulation (TOMACS) , vol.7 , Issue.1 , pp. 104-130
    • Falsafi, B.1    Wood, D.A.2
  • 68
    • 0022681148 scopus 로고
    • How not to lie with statistics: The correct way to summarize benchmark results
    • March DOI: 10.1145/5666.5673, 11
    • P. J. Fleming and J. J. Wallace. How not to lie with statistics: The correct way to summarize benchmark results. Communications of the ACM, 29(3):218-221, March 1986. DOI: 10.1145/5666.5673 11
    • (1986) Communications of the ACM , vol.29 , Issue.3 , pp. 218-221
    • Fleming, P.J.1    Wallace, J.J.2
  • 69
    • 84976676590 scopus 로고
    • Parallel discrete event simulation
    • October DOI: 10.1145/84537.84545, 99
    • R. M.Fujimoto. Parallel discrete event simulation. Communications of the ACM,33(10):30-53, October 1990. DOI: 10.1145/84537.84545 99
    • (1990) Communications of the ACM , vol.33 , Issue.10 , pp. 30-53
    • Fujimoto, R.M.1
  • 71
    • 36849017400 scopus 로고    scopus 로고
    • Memory data flow modeling in statistical simulation for the efficient exploration of microprocessor design spaces
    • January 88
    • D. Genbrugge and L. Eeckhout. Memory data flow modeling in statistical simulation for the efficient exploration of microprocessor design spaces. IEEE Transactions on Computers, 57(10):41-54, January 2007. 88
    • (2007) IEEE Transactions on Computers , vol.57 , Issue.10 , pp. 41-54
    • Genbrugge, D.1    Eeckhout, L.2
  • 72
    • 74549142310 scopus 로고    scopus 로고
    • Chip multiprocessor design space exploration through statistical simulation
    • December DOI: 10.1109/TC.2009.77 90, 91
    • D. Genbrugge and L. Eeckhout. Chip multiprocessor design space exploration through statistical simulation. IEEE Transactions on Computers, 58(12):1668-1681, December 2009. DOI: 10.1109/TC.2009.77 90, 91
    • (2009) IEEE Transactions on Computers , vol.58 , Issue.12 , pp. 1668-1681
    • Genbrugge, D.1    Eeckhout, L.2
  • 79
    • 84971355456 scopus 로고    scopus 로고
    • Accelerated warmup for sampled microarchitecture simulation
    • March DOI: 10.1145/1061267.1061272, 75
    • J. W. Haskins Jr. and K. Skadron. Accelerated warmup for sampled microarchitecture simulation. ACM Transactions on Architecture and Code Optimization (TACO), 2(1):78-108, March 2005. DOI: 10.1145/1061267.1061272 75
    • (2005) ACM Transactions on Architecture and Code Optimization (TACO) , vol.2 , Issue.1 , pp. 78-108
    • Haskins Jr., J.W.1    Skadron, K.2
  • 81
    • 0034226001 scopus 로고    scopus 로고
    • SPEC CPU2000: Measuring CPU performance in the new millennium
    • July 17
    • J. L. Henning. SPEC CPU2000: Measuring CPU performance in the new millennium. IEEE Computer, 33(7):28-35, July 2000. 17
    • (2000) IEEE Computer , vol.33 , Issue.7 , pp. 28-35
    • Henning, J.L.1
  • 82
    • 48249118853 scopus 로고    scopus 로고
    • Amdahl's law in the multicore era
    • July 31
    • M. D.Hill and M. R. Marty. Amdahl's law in the multicore era. IEEE Computer,41(7):33-38, July 2008. 31
    • (2008) IEEE Computer , vol.41 , Issue.7 , pp. 33-38
    • Hill, M.D.1    Marty, M.R.2
  • 83
    • 0024903997 scopus 로고
    • Evaluating associativity in CPU caches
    • DOI 10.1109/12.40842
    • M. D. Hill and A. J. Smith. Evaluating associativity in CPU caches. IEEE Transactions on Computers, 38(12):1612-1630, December 1989. DOI: 10.1109/12.40842 54, 87 (Pubitemid 20642724)
    • (1989) IEEE Transactions on Computers , vol.38 , Issue.12 , pp. 1612-1630
    • Hill Mark, D.1    Smith Alan Jay2
  • 84
    • 70450231944 scopus 로고    scopus 로고
    • An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness
    • June 46
    • S. Hong and H. Kim. An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 152-163, June 2008. 46
    • (2008) Proceedings of the International Symposium on Computer Architecture (ISCA) , pp. 152-163
    • Hong, S.1    Kim, H.2
  • 85
    • 34548329985 scopus 로고    scopus 로고
    • Microarchitecture-independent workload characterization
    • DOI 10.1109/MM.2007.56
    • K. Hoste and L. Eeckhout. Microarchitecture-independent workload characterization. IEEE Micro, 27(3):63-72, May 2007. DOI: 10.1109/MM.2007.56 20, 23 (Pubitemid 47337548)
    • (2007) IEEE Micro , vol.27 , Issue.3 , pp. 63-72
    • Hoste, K.1    Eeckhout, L.2
  • 86
    • 0032204476 scopus 로고    scopus 로고
    • Micro-processor power estimation using profile-driven program synthesis
    • November DOI: 10.1109/43.736182, 93
    • C. Hsieh and M. Pedram. Micro-processor power estimation using profile-driven program synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(11):1080-1089, November 1998. DOI: 10.1109/43.736182 93
    • (1998) IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol.17 , Issue.11 , pp. 1080-1089
    • Hsieh, C.1    Pedram, M.2
  • 87
    • 56449115895 scopus 로고    scopus 로고
    • Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
    • September DOI: 10.1109/IISWC.2008.4636101, 81, 92
    • C. Hughes and T. Li. Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis. In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), pages 163-172, September 2008. DOI: 10.1109/IISWC.2008.4636101 81, 92
    • (2008) Proceedings of the IEEE International Symposium on Workload Characterization (IISWC) , pp. 163-172
    • Hughes, C.1    Li, T.2
  • 88
    • 0036470602 scopus 로고    scopus 로고
    • Rsim: Simulating shared-memory multiprocessors with ILP processors
    • February 55
    • C. J. Hughes, V. S. Pai, P. Ranganathan, and S. V. Adve. Rsim: Simulating shared-memory multiprocessors with ILP processors. IEEE Computer, 35(2):40-49, February 2002. 55
    • (2002) IEEE Computer , vol.35 , Issue.2 , pp. 40-49
    • Hughes, C.J.1    Pai, V.S.2    Ranganathan, P.3    Adve, S.V.4
  • 90
    • 0006637419 scopus 로고    scopus 로고
    • Evaluation and generation of reduced traces for benchmarks
    • IBM Research Division, T. J. Watson Research Center October 93
    • V. S. Iyengar and L. H. Trevillyan. Evaluation and generation of reduced traces for benchmarks. Technical Report RC 20610, IBM Research Division, T. J. Watson Research Center, October 1996. 93
    • (1996) Technical Report RC 20610
    • Iyengar, V.S.1    Trevillyan, L.H.2
  • 93
    • 28444484731 scopus 로고    scopus 로고
    • More on finding a single number to indicate overall performance of a benchmark suite
    • 1-14 September 11, 12
    • L. K. John. More on finding a single number to indicate overall performance of a benchmark suite. ACM SIGARCH Computer Architecture News, 32(4):1-14, September 2004. 11, 12
    • (2004) ACM SIGARCH Computer Architecture News , vol.32 , Issue.4
    • John, L.K.1
  • 94
    • 77954934077 scopus 로고    scopus 로고
    • L. K. John and L. Eeckhout, editors. CRC Press, Taylor and Francis
    • L. K. John and L. Eeckhout, editors. Performance Evaluation and Benchmarking. CRC Press, Taylor and Francis, 2006. xi
    • (2006) Performance Evaluation and Benchmarking
  • 95
    • 0035248152 scopus 로고    scopus 로고
    • Lossless trace compression
    • DOI 10.1109/12.908991
    • E. E. Johnson, J. Ha, and M. B. Zaidi. Lossless trace compression. IEEE Transactions on Computers, 50(2):158-173, February 2001. DOI: 10.1109/12.908991 54 (Pubitemid 32286559)
    • (2001) IEEE Transactions on Computers , vol.50 , Issue.2 , pp. 158-173
    • Johnson, E.E.1    Ha, J.2    Zaidi, M.B.3
  • 99
    • 33646486530 scopus 로고    scopus 로고
    • Measuring benchmark similarity using inherent program characteristics
    • June DOI: 10.1109/TC.2006.85 23, 62
    • A. Joshi, A. Phansalkar, L. Eeckhout, and L. K. John. Measuring benchmark similarity using inherent program characteristics. IEEE Transactions on Computers,55(6):769-782, June 2006. DOI: 10.1109/TC.2006.85 23, 62
    • (2006) IEEE Transactions on Computers,55 , vol.6 , pp. 769-782
    • Joshi, A.1    Phansalkar, A.2    Eeckhout, L.3    John, L.K.4
  • 106
    • 0028445155 scopus 로고
    • A comparison of trace-sampling techniques for multi-megabyte caches
    • June DOI: 10.1109/12.286300 74, 75
    • R. E. Kessler, M. D. Hill, and D. A. Wood. A comparison of trace-sampling techniques for multi-megabyte caches. IEEE Transactions on Computers, 43(6):664-675, June 1994. DOI: 10.1109/12.286300 74, 75
    • (1994) IEEE Transactions on Computers , vol.43 , Issue.6 , pp. 664-675
    • Kessler, R.E.1    Hill, M.D.2    Wood., D.A.3
  • 108
    • 20344374162 scopus 로고    scopus 로고
    • Niagara: A 32-way multithreaded SPARC processor
    • March/April DOI: 10.1109/MM.2005.35, 7
    • P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-way multithreaded SPARC processor. IEEE Micro, 25(2):21-29, March/April 2005. DOI: 10.1109/MM.2005.35 7
    • (2005) IEEE Micro , vol.25 , Issue.2 , pp. 21-29
    • Kongetira, P.1    Aingaran, K.2    Olukotun., K.3
  • 111
    • 0018030656 scopus 로고
    • Performance evaluation of highly concurrent computers by deterministic simulation
    • November DOI: 10.1145/359642.359646, 81
    • B. Kumar and E. S. Davidson. Performance evaluation of highly concurrent computers by deterministic simulation. Communications of the ACM, 21(11):904-913, November 1978. DOI: 10.1145/359642.359646 81
    • (1978) Communications of the ACM , vol.21 , Issue.11 , pp. 904-913
    • Kumar, B.1    Davidson., E.S.2
  • 113
    • 0024107186 scopus 로고
    • Accurate low-cost methods for performance evaluation of cache memory systems
    • November DOI: 10.1109/12.8699, 64
    • S. Laha, J. H. Patel, and R. K. Iyer. Accurate low-cost methods for performance evaluation of cache memory systems. IEEE Transactions on Computers, 37(11):1325-1336, November 1988. DOI: 10.1109/12.8699 64
    • (1988) IEEE Transactions on Computers , vol.37 , Issue.11 , pp. 1325-1336
    • Laha, S.1    Patel, J.H.2    Iyer., R.K.3
  • 130
    • 85008034312 scopus 로고    scopus 로고
    • Efficiently evaluating speedup using sampled processor simulation
    • September 70
    • Y. Luo and L. K. John. Efficiently evaluating speedup using sampled processor simulation. Computer Architecture Letters, 4, September 2004. 70
    • (2004) Computer Architecture Letters , vol.4
    • Luo, Y.1    John., L.K.2
  • 131
    • 26244457143 scopus 로고    scopus 로고
    • SMA: A self-monitored adaptive warmup scheme for microprocessor simulation
    • October DOI: 10.1007/s10766-005-7305-9, 75
    • Y. Luo, L. K. John, and L. Eeckhout. SMA: A self-monitored adaptive warmup scheme for microprocessor simulation. International Journal on Parallel Programming, 33(5):561-581, October 2005. DOI: 10.1007/s10766-005-7305-9 75
    • (2005) International Journal on Parallel Programming , vol.33 , Issue.5 , pp. 561-581
    • Luo, Y.1    John, L.K.2    Eeckhout., L.3
  • 134
    • 47349130731 scopus 로고    scopus 로고
    • War of the benchmark means: Time for a truce
    • September DOI: 10.1145/1040136.1040137 11, 13
    • J. R. Mashey. War of the benchmark means: Time for a truce. ACM SIGARCH Computer Architecture News, 32(4):1-14, September 2004. DOI: 10.1145/1040136.1040137 11, 13
    • (2004) ACM SIGARCH Computer Architecture News , vol.32 , Issue.4 , pp. 1-14
    • Mashey., J.R.1
  • 135
    • 0014701246 scopus 로고
    • Evaluation techniques for storage hierarchies
    • June DOI: 10.1147/sj.92.0078 54, 87
    • R. L. Mattson, J. Gecsei, D. R. Slutz, and I. L. Traiger. Evaluation techniques for storage hierarchies. IBM Systems Journal, 9(2):78-117, June 1970. DOI: 10.1147/sj.92.0078 54, 87
    • (1970) IBM Systems Journal , vol.9 , Issue.2 , pp. 78-117
    • Mattson, R.L.1    Gecsei, J.2    Slutz, D.R.3    Traiger., I.L.4
  • 145
    • 53149144677 scopus 로고    scopus 로고
    • Empirical versus mechanistic modelling: Comparison of an artificial neural network to a mechanistically based model for quantitative structure pharmacokinetic relationships of a homologous series of barbiturates
    • December 32
    • I. Nestorov, M. Rowland, S. T. Hadjitodorov, and I. Petrov. Empirical versus mechanistic modelling: Comparison of an artificial neural network to a mechanistically based model for quantitative structure pharmacokinetic relationships of a homologous series of barbiturates. The AAPS Journal, 1(4):5-13, December 1999. 32
    • (1999) The AAPS Journal , vol.1 , Issue.4 , pp. 5-13
    • Nestorov, I.1    Rowland, M.2    Hadjitodorov, S.T.3    Petrov., I.4
  • 150
    • 52949090653 scopus 로고    scopus 로고
    • Statistical simulation of symmetric multiprocessor systems
    • April DOI: 10.1109/SIMSYM.2002.1000093, 91
    • S. Nussbaum and J. E. Smith. Statistical simulation of symmetric multiprocessor systems. In Proceedings of the 35th Annual Simulation Symposium 2002, pages 89-97, April 2002. DOI: 10.1109/SIMSYM.2002.1000093 91
    • (2002) Proceedings of the 35th Annual Simulation Symposium 2002 , pp. 89-97
    • Nussbaum, S.1    Smith., J.E.2
  • 156
    • 56449096977 scopus 로고    scopus 로고
    • Reproducible simulation of multi-threaded workloads for architecture design space exploration
    • September DOI: 10.1109/IISWC.2008.4636102, 59
    • C. Pereira, H. Patil, and B. Calder. Reproducible simulation of multi-threaded workloads for architecture design space exploration. In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), pages 173-182, September 2008. DOI: 10.1109/IISWC.2008.4636102 59
    • (2008) Proceeings of the IEEE International Symposium on Workload Characterization (IISWC) , pp. 173-182
    • Pereira, C.1    Patil, H.2    Calder., B.3
  • 162
    • 77954894309 scopus 로고    scopus 로고
    • Evolve or die: Making SPEC⣙s CPU suite relevant today and tomorrow
    • October Invited presentation DOI: 10.1109/IISWC.2006.302735, 21
    • J. Reilly. Evolve or die: Making SPEC⣙s CPU suite relevant today and tomorrow. IEEE International Symposium on Workload Characterization (IISWC), October 2006. Invited presentation. DOI: 10.1109/IISWC.2006.302735 21
    • (2006) IEEE International Symposium on Workload Characterization (IISWC)
    • Reilly., J.1
  • 164
    • 0041633624 scopus 로고    scopus 로고
    • Instruction set compiled simulation: A technique for fast and flexible instruction set simulation
    • June DOI: 10.1145/775832.776026, 72
    • M. Reshadi, P. Mishra, and N. D. Dutt. Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. In Proceedings of the 40th Design Automation Conference (DAC), pages 758-763, June 2003. DOI: 10.1145/775832.776026 72
    • (2003) Proceedings of the 40th Design Automation Conference (DAC) , pp. 758-763
    • Reshadi, M.1    Mishra, P.2    Dutt., N.D.3
  • 166
    • 0015490730 scopus 로고
    • The inhibition of potential parallelism by conditional jumps
    • December DOI: 10.1109/T-C.1972.223514, 35
    • E. M. Riseman and C. C. Foster. The inhibition of potential parallelism by conditional jumps. IEEE Transactions on Computers, C-21(12):1405-1411, December 1972. DOI: 10.1109/T-C.1972.223514 35
    • (1972) IEEE Transactions on Computers , vol.C-21 , Issue.12 , pp. 1405-1411
    • Riseman, E.M.1    Foster., C.C.2
  • 172
    • 0033220924 scopus 로고    scopus 로고
    • Branch prediction, instruction-window size, and cache size: Performance tradeoffs and simulation techniques
    • November DOI: 10.1109/12.811115, 67
    • K. Skadron, P. S. Ahuja, M. Martonosi, and D. W. Clark. Branch prediction, instruction-window size, and cache size: Performance tradeoffs and simulation techniques. IEEE Transactions on Computers, 48(11):1260-1281, November 1999. DOI: 10.1109/12.811115 67
    • (1999) IEEE Transactions on Compuers , vol.48 , Issue.11 , pp. 1260-1281
    • Skadron, K.1    Ahuja, P.S.2    Martonosi, M.3    Clark., D.W.4
  • 173
    • 0024091632 scopus 로고
    • Characterizing computer performance with a single number
    • October DOI: 10.1145/63039.63043, 11
    • J. E. Smith. Characterizing computer performance with a single number. Communications of the ACM, 31(10):1202-1206, October 1988. DOI: 10.1145/63039.63043 11
    • (1988) Communications of the ACM , vol.31 , Issue.10 , pp. 1202-1206
    • Smith., J.E.1
  • 180
    • 43049128224 scopus 로고    scopus 로고
    • An instruction throughput model of superscalar processors
    • March DOI: 10.1109/TC.2007.70817, 45
    • T. M.Taha and D. S. Wills. An instruction throughput model of superscalar processors. IEEE Transactions on Computers, 57(3):389-403, March 2008. DOI: 10.1109/TC.2007.70817 45
    • (2008) IEEE Transactions on Computers , vol.57 , Issue.3 , pp. 389-403
    • Taha, T.M.1    Wills., D.S.2
  • 184
    • 33947713690 scopus 로고    scopus 로고
    • Efficient sampling startup for SimPoint
    • July DOI: 10.1109/MM.2006.68, 73
    • M. Van Biesbrouck, B. Calder, and L. Eeckhout. Efficient sampling startup for SimPoint. IEEE Micro, 26(4):32-42, July 2006. DOI: 10.1109/MM.2006.68 73
    • (2006) IEEE Micro , vol.26 , Issue.4 , pp. 32-42
    • Van Biesbrouck, M.1    Calder, B.2    Eeckhout., L.3
  • 190
    • 33748289310 scopus 로고    scopus 로고
    • SIMFLEX: Statistical sampling of computer system simulation
    • DOI 10.1109/MM.2006.79
    • T.F.Wenisch,R.E.Wunderlich,M.Ferdman,A.Ailamaki,B.Falsafi,and J. C.Hoe. SimFlex: Statistical sampling of computer system simulation. IEEE Micro, 26(4):18-31, July 2006. DOI: 10.1109/MM.2006.79 7, 55, 66, 78, 79, 95 (Pubitemid 46504886)
    • (2006) IEEE Micro , vol.26 , Issue.4 , pp. 18-30
    • Wenisch, T.F.1    Wunderlich, R.E.2    Ferdman, M.3    Ailamaki, A.4    Falsafi, B.5    Hoe, J.C.6
  • 194


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.