Accurate functional-first multicore simulators

IEEE Computer Architecture Letters

Volumn 8, Issue 2, 2010, Pages 64-67

  Chiou, Derek ^a   Angepat, Hari ^a   Patil, Nikhil ^a   Sunwoo, Dam ^a  

^a The University of Texas at Austin

Author keywords

And Visualization; Integration and modeling; Modeling; Modeling of computer architecture; Modeling techniques; Multi core single chip multiprocessors; Parallel; Parallel Architectures; Performance Analysis and Design Aids; Simulation; System architectures

Indexed keywords

CHIP MULTIPROCESSOR; INTEGRATION AND MODELING; MODELING OF COMPUTER ARCHITECTURE; PARALLEL; PERFORMANCE ANALYSIS AND DESIGN AIDS; SIMULATION SYSTEMS;

COMPUTERS; MULTIPROCESSING SYSTEMS; SIMULATORS; VISUALIZATION;

PARALLEL ARCHITECTURES;

EID: 75449097194     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2009.44     Document Type: Article

References (17)

1. D. F. Bacon and S. C. Goldstein, "Hardware-assisted replay of multiprocessor programs," in Proceedings of the ACM/ONR Workshop on Parallel and Distributed Debugging, 1991.
2. R. Bhargava, L. Barnes, and B. Sander, "Amd," personal email communication.
3. N. L. Binkert, E. G. Hallnor, and S. K. Reinhardt, "Network- Oriented Full-System Simulation using M5," in Sixth Workshop on Computer Architecture Evaluation using Commerical Workloads, Feb. 2003.
4. D. Chiou, D. Sunwoo, J. Kim, N. A. Patil, W. H. Reinhart, D. E. Johnson, J. Keefe, and H. Angepat, "FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators," in Proceedings of MICRO, Dec. 2007.
5. D. Chiou, "FAST: FPGA-based Acceleration of Simulator Timing models," in Proceedings of the first Workshop on Architecture Research using FPGA Platforms, held in conjunction with HPCA-11, San Francisco, CA, Feb. 2005.
6. D. Chiou, H. Sanjeliwala, D. Sunwoo, J. Z. Xu, and N. Patil, "FPGA-based Fast, Cycle-Accurate, Full-System Simulators," in Proceedings of the second Workshop on Architecture Research using FPGA Platforms, held in conjunction with HPCA-12, Austin, TX, Feb. 2006.
7. D. Chiou, D. Sunwoo, J. Kim, N. A. Patil, W. H. Reinhart, D. E. Johnson, and Z. Xu, "The FAST Methodology for High- Speed SoC/Computer Simulation," in Proceedings of International Conference on Computer-Aided Design (ICCAD), Nov. 2007.
8. J. Emer, "Intel," personal communication, Jan. 2008.
9. A. Hilton and A. Roth, "Decoupled Store Completion/Silent Deterministic Replay: Enabling Scalable Data Memory for CPR/CFP Processors," in ISCA, Jun. 2009.
10. D. R. Hower and M. D. Hill, "Rerun: Exploiting Episodes for Lightweight Memory Race Recording," in ISCA, Jun. 2008.
11. L. Lamport, "How to make a multiprocessor that correctly executes multiprocess programs," IEEE Transactions on Computers, vol.28, no.9, pp. 690-691, Sep. 1979.
12. M. M. K. Martin, D. J. Sorin, H. W. Cain, M. D. Hill, and M. H. Lipasti, "Correctly Implementing Value Prediction in Microprocessors that Support Multithreading or Multiprocessing," in MICRO, Dec. 2001.
13. P. Montesinos, L. Ceze, and J. Torrellas, "Delorean: Recording and deterministically replaying shared-memory multiprocessor execution effciently," in ISCA, 2008, pp. 289-300.
14. S. Narayanasamy, G. Pokam, and B. Calder, "Bugnet: Continuously recording program execution for deterministic replay debugging," in ISCA, 2005, pp. 284-295.
15. E. Schnarr and J. R. Larus, "Fast out-of-order processor simulation using memoization," in Proceedings of the Eight International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 1998, pp. 283-294.
16. D. Sunwoo, J. Kim, and D. Chiou, "QUICK: A Flexible Full-System Functional Model," in IEEE Symposium on Performance Analysis of Software and Systems (ISPASS), Apr. 2009, pp. 249-258.
17. M. Xu, R. Bodik, and M. D. Hill, "A "flight data recorder" for enabling full-system multiprocessor deterministic replay," in ISCA, 2003, pp. 122-135.