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Volumn 42, Issue 2, 2008, Pages 36-47

Efficiency trends and limits from comprehensive microarchitectural adaptivity

Author keywords

Adaptivity; Efficiency; Inference; Microarchitecture; Performance; Power; Reconfigurablity; Regression; Simulation; Statistics

Indexed keywords

COMPUTATIONAL EFFICIENCY; COMPUTER HARDWARE; COMPUTER SIMULATION; HEURISTIC METHODS; OPTIMIZATION; REGRESSION ANALYSIS; STATISTICS;

EID: 77957818268     PISSN: 01635980     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1353535.1346288     Document Type: Conference Paper
Times cited : (17)

References (35)
  • 3
    • 33749079198 scopus 로고    scopus 로고
    • Bioperf: A benchmark suite to evaluate high-performance computer architecture on bioinformatics applications
    • October
    • D. Bader, Y. Li, T. Li, and V. Sachdeva. Bioperf: A benchmark suite to evaluate high-performance computer architecture on bioinformatics applications. In IEEE International Symposium on Workload Characterization, October 2005.
    • (2005) IEEE International Symposium on Workload Characterization
    • Bader, D.1    Li, Y.2    Li, T.3    Sachdeva, V.4
  • 6
    • 0034316092 scopus 로고    scopus 로고
    • Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors
    • Nov/Dec
    • D. Brooks and et. al. Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors. IEEE Micro, 20(6):26-44, Nov/Dec 2000.
    • (2000) IEEE Micro , vol.20 , Issue.6 , pp. 26-44
    • Brooks, D.1    and et., al.2
  • 10
  • 13
    • 2342591856 scopus 로고    scopus 로고
    • The intel pentium m processor: Micorarchitecture and performance
    • May
    • S. Gochman, R. Ronen, and et al. The intel pentium m processor: Micorarchitecture and performance. Intel Technology Journal, 7(2), May 2003.
    • (2003) Intel Technology Journal , vol.7 , Issue.2
    • Gochman, S.1    Ronen, R.2    and et, al.3
  • 15
    • 0034226001 scopus 로고    scopus 로고
    • Spec cpu2000: Measuring cpu performance in the new millenium
    • July
    • J. Henning. Spec cpu2000: Measuring cpu performance in the new millenium. IEEE Computer, July 2000.
    • (2000) IEEE Computer
    • Henning, J.1
  • 17
    • 0035694233 scopus 로고    scopus 로고
    • Saving energy with architectural and frequency adaptations for multimedia applications
    • December
    • C. Hughes, J. Srinivasan, and S. Adve. Saving energy with architectural and frequency adaptations for multimedia applications. In International Symposium on Micwarchitecture, December 2001.
    • (2001) International Symposium on Micwarchitecture
    • Hughes, C.1    Srinivasan, J.2    Adve, S.3
  • 23
    • 40349098498 scopus 로고    scopus 로고
    • Mitigating the impact of process variations on cpu register file and execution units
    • December
    • X. Liang and D. Brooks. Mitigating the impact of process variations on cpu register file and execution units. In International Symposium on Micwarchitecture, December 2006.
    • (2006) International Symposium on Micwarchitecture
    • Liang, X.1    Brooks, D.2
  • 25
    • 0032683935 scopus 로고    scopus 로고
    • Environment for PowerPC microarchitecture exploration
    • May/June
    • M. Moudgill, J. Wellman, and J. Moreno. Environment for PowerPC microarchitecture exploration. IEEE Micro, 19(3):9-14, May/June 1999.
    • (1999) IEEE Micro , vol.19 , Issue.3 , pp. 9-14
    • Moudgill, M.1    Wellman, J.2    Moreno, J.3
  • 27
    • 0035691607 scopus 로고    scopus 로고
    • Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources
    • December
    • D. Ponomarev, G. Kucuk, and K. Ghose. Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. In International. Symposium on Microarchitecture, December 2001.
    • (2001) International. Symposium on Microarchitecture
    • Ponomarev, D.1    Kucuk, G.2    Ghose, K.3
  • 30
    • 1642330988 scopus 로고    scopus 로고
    • An. integrated cache timing, power, and area model
    • Technical Report 2001/2, Compaq Computer Corporation, August
    • P. Shivakumar and N. Jouppi. An. integrated cache timing, power, and area model. In Technical Report 2001/2, Compaq Computer Corporation, August 2001.
    • (2001)
    • Shivakumar, P.1    Jouppi, N.2
  • 32
    • 0029179077 scopus 로고    scopus 로고
    • S. Woo, M.. Ohara, E. Torrie, J. Singh, and A. Gupta. The SPLASH-2 programs: Characterization, and methodological considerations. In International Symposium on Computer Architecture, June 1995.
    • S. Woo, M.. Ohara, E. Torrie, J. Singh, and A. Gupta. The SPLASH-2 programs: Characterization, and methodological considerations. In International Symposium on Computer Architecture, June 1995.
  • 34
    • 0003720587 scopus 로고    scopus 로고
    • Inherently lower-power high-performance superscalar architectures
    • March
    • V. Zyuban. Inherently lower-power high-performance superscalar architectures. In Ph.D. Thesis, University of Notre Dame, March 2000.
    • (2000) Ph.D. Thesis, University of Notre Dame
    • Zyuban, V.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.