-
2
-
-
47349088877
-
Performance characterization of SPEC CPU benchmarks on intel's core microarchitecture based processor
-
S. Bird, A. Phansalkar, L. K. John, A. Mericas, and R. Indukuru. Performance characterization of SPEC CPU benchmarks on intel's core microarchitecture based processor. In SPEC Benchmark Workshop, 2007.
-
(2007)
SPEC Benchmark Workshop
-
-
Bird, S.1
Phansalkar, A.2
John, L.K.3
Mericas, A.4
Indukuru, R.5
-
4
-
-
0033719421
-
Wattch: A framework for architectural-level power analysis and optimizations
-
D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In ISCA-27, 2000.
-
(2000)
ISCA-27
-
-
Brooks, D.1
Tiwari, V.2
Martonosi, M.3
-
5
-
-
34547146937
-
-
J. Cavazos, C. Dubach, F. Agakov, E. Bonilla, M. F. P. O'Boyle, G. Fursin, and O. Temam. Automatic performance model construction for the fast software exploration of new hardware designs. In CASES, 2006.
-
J. Cavazos, C. Dubach, F. Agakov, E. Bonilla, M. F. P. O'Boyle, G. Fursin, and O. Temam. Automatic performance model construction for the fast software exploration of new hardware designs. In CASES, 2006.
-
-
-
-
6
-
-
47349099432
-
-
L. Eeckhout, R. H. B. Jr., B. Stougie, K. D. Bosschere, and L. K. John. Control flow modeling in statistical simulation for accurate and efficient processor design studies. In ISCA-31, 2004.
-
L. Eeckhout, R. H. B. Jr., B. Stougie, K. D. Bosschere, and L. K. John. Control flow modeling in statistical simulation for accurate and efficient processor design studies. In ISCA-31, 2004.
-
-
-
-
7
-
-
34047158789
-
Efficient design space exploration of high performance embedded out-of-order processors
-
S. Eyerman, L. Eeckhout, and K. D. Bosschere. Efficient design space exploration of high performance embedded out-of-order processors. In DATE, 2006.
-
(2006)
DATE
-
-
Eyerman, S.1
Eeckhout, L.2
Bosschere, K.D.3
-
8
-
-
34247169237
-
Performance prediction based on inherent program similarity
-
K. Hoste, A. Phansalkar, L. Eeckhout, A. Georges, L. K. John, and K. D. Bosschere. Performance prediction based on inherent program similarity. In PACT, 2006.
-
(2006)
PACT
-
-
Hoste, K.1
Phansalkar, A.2
Eeckhout, L.3
Georges, A.4
John, L.K.5
Bosschere, K.D.6
-
11
-
-
34547417098
-
Efficiently exploring architectural design spaces via predictive modeling
-
E. İpek, S. A. McKee, R. Caruana, B. R. de Supinski, and M. Schulz. Efficiently exploring architectural design spaces via predictive modeling. In ASPLOS-XII, 2006.
-
(2006)
ASPLOS-XII
-
-
İpek, E.1
McKee, S.A.2
Caruana, R.3
de Supinski, B.R.4
Schulz, M.5
-
12
-
-
33748863916
-
Construction and use of linear regression models for processor performance analysis
-
February
-
P. J. Joseph, K. Vaswani, and M. J. Thazhuthaveetil. Construction and use of linear regression models for processor performance analysis. In HPCA-12, February 2006.
-
(2006)
HPCA-12
-
-
Joseph, P.J.1
Vaswani, K.2
Thazhuthaveetil, M.J.3
-
15
-
-
47849123249
-
Using predictive modeling for cross-program design space exploration in multicore systems
-
S. Khan, P. Xekalakis, J. Cavazos, and M. Cintra. Using predictive modeling for cross-program design space exploration in multicore systems. In PACT, 2007.
-
(2007)
PACT
-
-
Khan, S.1
Xekalakis, P.2
Cavazos, J.3
Cintra, M.4
-
16
-
-
34547288276
-
Accurate and efficient regression modeling for microarchitectural performance and power prediction
-
B. C. Lee and D. M. Brooks. Accurate and efficient regression modeling for microarchitectural performance and power prediction. In ASPLOS-XII, 2006.
-
(2006)
ASPLOS-XII
-
-
Lee, B.C.1
Brooks, D.M.2
-
17
-
-
34547702258
-
Illustrative design space studies with microarchitectural regression models
-
B. C. Lee and D. M. Brooks. Illustrative design space studies with microarchitectural regression models. In HPCA-13, 2007.
-
(2007)
HPCA-13
-
-
Lee, B.C.1
Brooks, D.M.2
-
18
-
-
34748909426
-
Methods of inference and learning for performance modeling of parallel applications
-
B. C. Lee, D. M. Brooks, B. R. de Supinski, M. Schulz, K. Singh, and S. A. McKee. Methods of inference and learning for performance modeling of parallel applications. In PPoPP-12, 2007.
-
(2007)
PPoPP-12
-
-
Lee, B.C.1
Brooks, D.M.2
de Supinski, B.R.3
Schulz, M.4
Singh, K.5
McKee, S.A.6
-
19
-
-
85016676932
-
Theoretical modeling of superscalar processor performance
-
D. B. Noonburg and J. P. Shen. Theoretical modeling of superscalar processor performance. In MICRO-27, 1994.
-
(1994)
MICRO-27
-
-
Noonburg, D.B.1
Shen, J.P.2
-
20
-
-
47349106603
-
Efficient performance prediction for modern microprocessors
-
D. Ofelt and J. L. Hennessy. Efficient performance prediction for modern microprocessors. In SIGMETRICS, 2000.
-
(2000)
SIGMETRICS
-
-
Ofelt, D.1
Hennessy, J.L.2
-
21
-
-
0033719951
-
Hls: Combining statistical and symbolic simulation to guide microprocessor designs
-
M. Oskin, F. T. Chong, and M. Farrens. Hls: combining statistical and symbolic simulation to guide microprocessor designs. In ISCA-27, 2000.
-
(2000)
ISCA-27
-
-
Oskin, M.1
Chong, F.T.2
Farrens, M.3
-
22
-
-
21144433616
-
Hlspower: Hybrid statistical modeling of the superscalar power-performance design space
-
R. Rao, M. Oskin, and F. T. Chong. Hlspower: Hybrid statistical modeling of the superscalar power-performance design space. In HiPC, 2002.
-
(2002)
HiPC
-
-
Rao, R.1
Oskin, M.2
Chong, F.T.3
-
23
-
-
0038346244
-
Smarts: Accelerating microarchitecture simulation via rigorous statistical sampling
-
B. F. Roland E. Wunderlich, Thomas F. Wenisch and J. C. Hoe. Smarts: Accelerating microarchitecture simulation via rigorous statistical sampling. In ISCA-30, 2003.
-
(2003)
ISCA-30
-
-
Roland, B.F.1
Wunderlich, E.2
Wenisch, T.F.3
Hoe, J.C.4
-
25
-
-
47349087554
-
-
The Standard Performance Evaluation Corporation (SPEC) CPU 2000 Benchmark Suite. http://www.spec.org/cpu2000/.
-
The Standard Performance Evaluation Corporation (SPEC) CPU 2000 Benchmark Suite. http://www.spec.org/cpu2000/.
-
-
-
-
26
-
-
34547664408
-
Cacti 4.0
-
Technical Report HPL-2006-86, HP Laboratories Palo Alto
-
D. Tarjan, S. Thoziyoor, and N. P. Jouppi. Cacti 4.0. Technical Report HPL-2006-86, HP Laboratories Palo Alto, 2006.
-
(2006)
-
-
Tarjan, D.1
Thoziyoor, S.2
Jouppi, N.P.3
-
27
-
-
34547681859
-
-
K. Vaswani, M. J. Thazhuthaveetil, Y. N. Srikant, and P. J. Joseph. Microarchitecture sensitive empirical models for compiler optimizations. In CGO, 2007.
-
K. Vaswani, M. J. Thazhuthaveetil, Y. N. Srikant, and P. J. Joseph. Microarchitecture sensitive empirical models for compiler optimizations. In CGO, 2007.
-
-
-
|