Reproducible simulation of multi-threaded workloads for architecture design exploration

2008 IEEE International Symposium on Workload Characterization, IISWC'08

Volumn , Issue , 2008, Pages 173-182

  Pereira, Cristiano ^a,b   Patil, Harish ^b   Calder, Brad ^a,c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b INTEL CORPORATION   (United States)

^c MICROSOFT   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MULTIPROCESSING SYSTEMS;

ARCHITECTURE CONFIGURATIONS; ARCHITECTURE DESIGNS; BINARY INSTRUMENTATIONS; EXECUTION PATHS; MULTI-PROCESSORS; MULTIPROCESSOR ARCHITECTURES; SIMULATION RESULTS; SIMULATION TECHNIQUES;

ARCHITECTURE;

EID: 56449096977     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IISWC.2008.4636102     Document Type: Conference Paper

References (17)

1. A. R. Alameldeen and D. A. Wood. Variability in architectural simulations of multi-threaded commercial workloads. In Annual International Symposium on High Performance Computer Architecture (HPCA-9), 2003.
2. Vishal Aslot, Max J. Domeika, Rudolf Eigenmann, Greg Gaertner, Wesley B. Jones, and Bodo Parady. Specomp: A new benchmark suite for measuring parallel computer performance. In WOMPAT '01: Proceedings of the International Workshop on OpenMP Applications and Tools, pages 1-10, London, UK, 2001. Springer-Verlag.
3. Magnus Ekman and Per Stenstrom. Enhancing multiprocessor architecture simulation speed using matched-pair comparison. In Proceedings of the International Symposium on Performance Analysis of Systems and Software, 2005.
4. J. Emer, P. Ahuja, E. Borch, A. Klauser, C.K. Luk, S. Manne, S. S. Mukherjee, H. Patil, S. Wallace, N. Binkert, R. Espasa, and T. Juan. Asim: A performance model framework. Computer, 35(2):68-76, 2002.
5. Kevin M. Lepak, Harold W. Cain, and Mikko H. Lipasti. Redeeming ipc as a performance metric for multithreaded programs. In PACT '03: Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques, page 232, Washington, DC, USA, 2003. IEEE Computer Society.
6. C. K Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: Building customized program analysis tools with dynamic instrumentation. In Programming Language Design and Implementation, Chicago, IL, June 2005.
7. Carl J. Mauer, Mark D. Hill, and David A. Wood. Full-system timing-first simulation. In SIGMETRICS '02: Proceedings of the 2002 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, pages 108-116, New York, NY, USA, 2002. ACM Press.
8. S. Narayanasamy, G. Pokam, and B. Calder. Bugnet: Continuously recording program execution for deterministic replay debugging. In ISCA, June 2005.
9. Satish Narayanasamy, Cristiano Pereira, Harish Patil, Robert Cohn, and Brad Calder. Automatic logging of operating system effects to guide application-level architecture simulation. In SIGMETRICS '06/Performance '06: Proceedings of the joint international conference on Measurement and modeling of computer systems, pages 216-227, New York, NY, USA, 2006. ACM Press.
10. R. H. B. Netzer. Optimal tracing and replay for debugging shared-memory parallel programs. In Proceedings of the ACM/ONR Workshop on Parallel and Distributed Debugging, pages 1-11, 1993.
11. Erez Perelman, Marzia Polito, Jean-Yves Bouguet, John Sampson, Brad Calder, and Carole Dulong. Detecting phases in parallel applications on shared memory architectures. In IEEE International Parallel and Distributed Processing Symposium, pages 25-29, 2006.
12. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In ASPLOS-X, October 2002.
13. Dean M. Tullsen and Jeffery A. Brown. Handling long-latency loads in a simultaneous multithreading processor. In MICRO 34: Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, pages 318-327, Washington, DC, USA, 2001. IEEE Computer Society.
14. Eric Tune, Dongning Liang, Dean M. Tullsen, and Brad Calder. Dynamic prediction of the critical dependence path. In Proceeedings of the 7th International Symposium On High Performance Computer Architecture, 2001.
15. Thomas F. Wenisch, Roland E. Wunderlich, Michael Ferdman, Anastassia Ailamaki, Babak Falsafi, and James C. Hoe. Simflex: Statistical sampling of computer system simulation. IEEE Micro, 26(4):18-31, 2006.
16. Roland E. Wunderlich, Thomas F Wenisch, Babak Falsafi, and James C. Hoe. SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling. In ISCA-30, June 2003.
17. M. Xu, R. Bodik, and M. Hill. A flight data recorder for enabling full-system multiprocessor deterministic replay. In 30th Annual International Symposium on Computer Architecture, San Diego, CA, 2003.