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Volumn 2003-January, Issue , 2003, Pages 26-34

Initial observations of the simultaneous multithreading Pentium 4 processor

Author keywords

[No Author keywords available]

Indexed keywords

MULTIPROGRAMMING; PARALLEL ARCHITECTURES; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; RECONFIGURABLE HARDWARE;

EID: 34547715870     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2003.1237999     Document Type: Conference Paper
Times cited : (89)

References (31)
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    • Converting thread-level parallelism into instruction level parallelism via simultaneous multithreading
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    • J. Lo, S. Eggers, J. Emer, H. Levy, R. Stamm, and D. Tullsen. Converting thread-level parallelism into instruction level parallelism via simultaneous multithreading. ACM Transactions on Computer Systems, 15(3):322-354, Aug. 1997.
    • (1997) ACM Transactions on Computer Systems , vol.15 , Issue.3 , pp. 322-354
    • Lo, J.1    Eggers, S.2    Emer, J.3    Levy, H.4    Stamm, R.5    Tullsen, D.6
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    • A benchmark evaluation of a multi-threaded RISC processor architecture
    • Aug
    • R. Prasadh and C.-L. Wu. A benchmark evaluation of a multi-threaded RISC processor architecture. In International Conference on Parallel Processing, pages I:84-91, Aug. 1991.
    • (1991) International Conference on Parallel Processing , pp. I:84-I:91
    • Prasadh, R.1    Wu, C.-L.2
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    • Shar, L.E.1    Davidson, E.S.2
  • 20
    • 84889036959 scopus 로고    scopus 로고
    • Identifying Bottlenecks in Multithreaded Superscalar Multiprocessors
    • chapter springer-verlag
    • U. Sigmund and T. Ungerer. Lecture Notes in Computer Science 1123:797-800, chapter Identifying Bottlenecks in Multithreaded Superscalar Multiprocessors. springer-verlag, 1996.
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    • Sigmund, U.1    Ungerer, T.2
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    • Architecture and implications of the HEP multiprocessor computer system
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    • Smith, B.1
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    • The MAJC architecture: A synthesis of parallelism and scalability
    • Nov
    • M. Tremblay, J. Chan, S. Chaudhry, A. W. Conigliaro, and S. S. Tse. The MAJC architecture: A synthesis of parallelism and scalability. IEEE Micro, 20(6), Nov. 2000.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.