Predicting inter-thread cache contention on a chip multi-processor architecture

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2005, Pages 340-351

  Chandra, Dhruba ^a   Guo, Fei ^a   Kim, Seongbeom ^a   Solihin, Yan ^a  

^a North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE SHARING; CHIP MULTIPROCESSORS (CMP); INDUCTIVE PROBABILITY MODELS; THREADS;

CACHE MEMORY; COMPUTER SIMULATION; ERROR ANALYSIS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; ONLINE SYSTEMS; PROBABILITY;

COMPUTER ARCHITECTURE;

EID: 21244474546     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2005.27     Document Type: Conference Paper

References (26)

1. A. Agarwal, M. Horowitz, and J. Hennessy. An Analytical Cache Model. ACM Trans. on Computer Systems, 1989.
2. J.-L. Baer and W.-H. Wang. On the Inclusion Properties for Multi-Level Cache Hierarchies. In Proc. of the Intl. Symp. on Computer Architecture, 1988.
3. C. Cascaval, L. DeRose, D. A. Padua, and D. Reed. Compile-Time Based Performance Prediction. In Proc. of the 12th Intl. Workshop on Languages and Compilers for Parallel Computing, 1999.
4. S. Chatterjee, E. Parker, P. Hanlon, and A. Lebeck. Exact analysis of the cache behavior of nested loops. In Proc.of ACM SIGPLAN Conf. on Programming Language Design and Implementation, 2001.
5. B. Fraguela, R. Doallo, and E. Zapata. Automatic analytical modeling for the estimation of cache misses. In Proc.of Intl. Conf. on Parallel Architectures and Compilation Techniques, 1999.
6. S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: a compiler framework for analyzing and tuning memory behavior. ACM Trans. on Programming Languages and Systems, 21(4):703-746, 1999.
7. S. Hily and A. Seznec. Contention on the 2nd level cache may limit the effectiveness of simultaneous multithreading. IRISA Tech. Rep. 1086, 1997.
8. IBM. IBM Power4 System Architecture White Paper, 2002.
9. J. Renau, et al. SESC. http://sesc.sourceforge.net, 2004.
10. M. Kharbutli, K. Irwin, Y. Solihin, and J. Lee. Using prime numbers for cache indexing to eliminate conflict misses. In Proc. of the Intl. Symp. on High Performance Computer Architecture, 2004.
11. S. Kim, D. Chandra, and Y. Solihin. Fair cache sharing and partitioning on a chip multi-processor architecture. In Proc. of the Intl. Conf. on Parallel Architecture and Compilation Techniques, 2004.
12. J. Lee, Y. Solihin, and J. Torrellas. Automatically Mapping Code on an Intelligent Memory Architecture. In 7th Intl. Symp. on High Performance Computer Architecture, 2001.
13. T. Leng, R. Ali, and J. Hsieh. A study of hyper-threading in high-performance computing clusters. Dell Power Solutions HPC Cluster Environment, pages 33-36, 2002.
14. R. L. Mattson, J. Gecsei, D. Slutz, and I. Traiger. Evaluation Techniques for Storage Hierarchies. IBM Systems Journal, 9(2), 1970.
15. T. Sherwood, S. Sair, and B. Calder. Phase tracking and prediction. In Proc. of the Intl. Symp. on Computer Architecture (ISCA), 2003.
16. A. Snavely and D. Tullsen. Symbiotic jobscheduling for a simultaneous multithreading processor. In Proc. of the Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, 2000.
17. A. Snavely, et al. Explorations in symbiosis on two multithreaded architectures. In Workshop on Multithreaded Execution, Architecture, and Compilation, 1999.
18. Y. Solihin, V. Lam, and J. Torrellas. Seal-tool: Pinpointing and quantifying scalability bottlenecks in dsm multiprocessors. In Supercomputing, 1999.
19. Y. Solihin, J. Lee, and J. Torrellas. Automatic Code Mapping on an Intelligent Memory Architecture. IEEE Trans. on Computers: special issue on Advances in High Performance Memory Systems, 2001.
20. Standard Performance Evaluation Corporation. Spec benchmarks, http://www.spec.org, 2000.
21. G. Suh, S. Devadas, and L. Rudolph. Analytical Cache Models with Applications to Cache Partitioning. In Proc. of Intl. Conf. on Supercomputing, 2001.
22. G. E. Suh, S. Devadas, and L. Rudolph. A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning. In Proc. of Intl. Symp. on High Performance Computer Architecture, 2002.
23. D. Thiebaut, H. Stone, and J. Wolf. Footprints in the cache. ACM Trans. on Computer Systems, 5(4), Nov. 1987.
24. X. Vera and J. Xue. Let's Study Whole-Program Cache Behaviour Analytically. In Proc. of Intl. Symp. on High Performance Computer Architecture, 2002.
25. D. Vianney. Hyper-threading speeds linux: Multiprocessor performance on a single processor. IBM DeveloperWorks, 2003.
26. H. J. Wassermann, O. M. Lubeck, Y. Luo, and F. Bas-setti. Performance Evaluation of the SGI Origin2000: A Memory-Centric Characterization of LANL ASCI Applications. In Supercomputing, 1997.