Combining trace sampling with single pass methods for efficient cache simulation

IEEE Transactions on Computers

Volumn 47, Issue 6, 1998, Pages 714-719

  Conte, Thomas M ^a,b   Hirsch, Mary Ann ^a,b   Hwu, Wen Mei W ^a,c  

^a IEEE   (United States)

^b North Carolina State University   (United States)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Performance analysis; Sampling techniques; Single pass algorithms; Stacking algorithms; Trace driven simulation

Indexed keywords

EID: 1842860791     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.689650     Document Type: Article

References (15)

1. R.L. Mattson, J. Gercsei, D.R. Slutz, and I.L. Traiger, "Evaluation Techniques for Storage Hierarchies," IBM Systems J., vol. 9, no. 2, pp. 78-117, 1970.
2. A. Agarwal, M. Horowitz, and J. Hennessy, "An Analytical Cache Model," ACM Trans. Computer Systems, vol. 7, pp. 184-215, May 1989.
3. A.J. Smith, "A Second Bibliography on Cache Memories," Computer Architecture News, vol. 19, pp. 138-153, June 1991.
4. I.L. Traiger and D.R. Slutz, "One-Pass Techniques for the Evaluation of Memory Hierarchies," IBM Research Report RJ892, IBM, San Jose, Calif., July 1971.
5. J.G. Thompson and A.J. Smith, "Efficient (Stack) Algorithms for Analysis of Write-Back and Sector Memories," ACM Trans. Computer Systems, vol. 7, pp. 78-117, Feb. 1989.
6. M.D. Hill and A.J. Smith, "Evaluating Associativity in CPU Caches," IEEE Trans. Computers, vol. 38, no. 12, pp. 1,612-1,530, Dec. 1989.
7. R.E. Kessler, M.D. Hill, and D.A. Wood, "A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches," IEEE Trans. Computers, vol. 43, no. 6, pp. 664-675, June 1994.
8. S. Laha, J.A. Patel, and R.K. Iyer, "Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems," IEEE Trans. Computers, vol. 37, no. 2, pp. 1,325-1,336, Feb. 1988.
9. H.S. Stone, High-Performance Computer Architecture. New York: Addison-Wesley, 1990.
10. K.R. Kaplan and R.O. Winder, "Cache-Based Computer Systems," Computer, vol. 6, pp. 30-36, Mar. 1973.
11. W.W. Hwu and T.M. Conte, "A Simulation Study of Simultaneous Vector Prefetch Performance in Multiprocessor Memory Subsystems," Proc. ACM SIGMETRICS '89 Conf. Measurement and Modeling of Computer Systems, p. 227, Berkeley, Calif., May 1989.
12. A.J. Smith, "Cache Memories," ACM Computing Surveys, vol. 14, no. 3, pp. 473-530, 1982.
13. T.M. Conte and W.W. Hwu, " Benchmark Characterization," Computer, pp. 48-56, Jan. 1991.
14. J.W.C. Fu and J.H. Patel, "How to Simulate 100 Billion References Cheaply," Technical Report CRHC-91-30, Center for Reliable and High-Performance Computing, Univ. of Illinois at Urbana-Champaign, Urbana, Ill., Nov. 1991.
15. W.W. Hwu and T.M. Conte, "The Susceptibility of Programs to Context Switching," IEEE Trans. Computers, vol. 43, no. 9, pp. 993-1,003, Sept. 1994.