An instruction throughput model of superscalar processors

IEEE Transactions on Computers

Volumn 57, Issue 3, 2008, Pages 389-403

  Taha, Tarek M ^a   Wills, D Scott ^b  

^a AMRL   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Analytical modeling; Modeling of computer architecture; Modeling techniques; Performance prediction; Superscalar architectures

Indexed keywords

COMPUTER ARCHITECTURE; LARGE SCALE SYSTEMS; SOFTWARE DESIGN; THROUGHPUT;

INSTRUCTION THROUGHPUT MODEL; SUPERSCALAR PROCESSOR;

PROGRAM PROCESSORS;

EID: 43049128224     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2007.70817     Document Type: Article

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