Balancing thoughput and fairness in SMT processors

2001 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2001

Volumn , Issue , 2001, Pages 164-171

  Luo, Kun ^a   Gummaraju, Jayanth ^b   Franklin, Manoj ^a  

^a UNIVERSITY OF MARYLAND   (United States)

^b Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MULTITASKING; PIPELINES; PROGRAM PROCESSORS; THROUGHPUT; TRANSMISSION CONTROL PROTOCOL;

BRANCH PREDICTION; EXECUTION MODEL; INSTRUCTION FETCH UNIT; INSTRUCTION QUEUE; MULTIPLE THREADS; PIPE-LINE SYSTEMS; SIMULTANEOUS MULTI-THREADING; SINGLE PROCESSORS;

PIPELINE PROCESSING SYSTEMS;

EID: 84962144701     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2001.990695     Document Type: Conference Paper

References (9)

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