QUICK: A flexible full-system functional model

ISPASS 2009 - International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2009, Pages 249-258

  Sunwoo, Dam ^a   Kim, Joonsoo ^a   Chiou, Derek ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CYCLE ACCURATE; FUNCTIONAL MODEL; FUNCTIONAL SIMULATORS; I/O OPERATIONS; INTERNET EXPLORERS; ON-THE-FLY; PERFORMANCE ANALYSIS; POWERPC; SIMULATION PERFORMANCE; WINDOWS XP; YOUTUBE;

COMPUTER OPERATING SYSTEMS; INTERCONNECTION NETWORKS;

SIMULATORS;

EID: 70349164524     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2009.4919656     Document Type: Conference Paper

References (16)

1. F. Bellard. QEMU, a Fast and Portable Dynamic Translator. In USENIX 2005 Annual Technical Conference, FREENIX Track, pages 41-46, 2005.
2. N. L. Binkert, E. G. Hallnor, and S. K. Reinhardt. Network-Oriented Full-System Simulation using M5. In Sixth Workshop on Computer Architecture Evaluation using Commerical Workloads, Feb. 2003.
3. D. Chiou, D. Sunwoo, J. Kim, N. A. Patil, W. H. Reinhart, D. E. Johnson, J. Keefe, and H. Angepat. FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators. In Proceedings of MICRO, Dec. 2007.
4. N. Dave, M. Pellauer, Arvind, and J. Emer. Implementing a Functional/Timing Partitioned Microprocessor Simulator with an FPGA. In Proceedings of the Workshop on Architecture Research using FPGA Platforms, held at HPCA-12, Feb. 2006.
5. J. Edler and M. D. Hill. Dinero IV Trace-Driven Uniprocessor Cache Simulator. web site: http://www.cs.wisc.edu/markhill/DineroIV.
6. J. Emer, P. Ahuja, E. Borch, A. Klauser, C. K. Luk, S. Manne, S. S. Mukherjee, H. Patil, S.Wallace, N. Binkert, R. Espasa, and T. Juan. Asim: A performance model framework. Computer, 35(2):68-76, 2002.
7. P. S. M. et al. Simics: A Full System Simulation Platform. Computer, pages 50-58, Feb. 2002.
8. A. Falcon, P. Faraboschi, and D. Ortega. Combining Simulation and Virtualization through Dynamic Sampling. In Proceedings of ISPASS, Apr. 2007.
9. Intel, www.intel.com/design/processor/manuals/253668.pdf. Intel 64 and IA-32 Architecture Software Developer's Manual, Volume 3A: System Programming Guide, Part 1, 2007.
10. K. P. Lawton. Bochs: A Portable PC Emulator for Unix/X. Linux J., 1996(29es):7, 1996.
11. C. J. Mauer, M. D. Hill, and D. A. Wood. Full-system timing-first simulation. In ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, pages 108-116, 2002.
12. E. Schnarr and J. R. Larus. Fast out-of-order processor simulation using memoization. In Proceedings of the Eight International Conference on Architectural Support for Programming Languages and Operating Systems, pages 283-294, Oct. 1998.
13. SimNow webpage. http://developer.amd.com/simnow.aspx.
14. J. Smith and A. Pleszkun. Implementation of precise interrupts in pipelined processors. In Proceedings of the 12th International Symposium on Computer Architecture, Jan. 1985.
15. E. L. T. Austin and D. Ernst. SimpleScalar: An Infrastructure for Computer System Modeling. Computer, 35(2):59-67, Feb. 2002.
16. M. T. Yourst. PTLSim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator. In Proceedings of ISPASS, Jan. 2007.