-
1
-
-
0024656760
-
An Analytical Cache Model
-
A. Agarwal, M. Horowitz, and J. Hennessy. An Analytical Cache Model. TOCS, 7(2): 184-215, 1989.
-
(1989)
TOCS
, vol.7
, Issue.2
, pp. 184-215
-
-
Agarwal, A.1
Horowitz, M.2
Hennessy, J.3
-
2
-
-
0026267802
-
An Effective On-chip Preloading Scheme to Reduce Data Access Penalty
-
J.-L. Baer and T.-F. Chen. An Effective On-chip Preloading Scheme to Reduce Data Access Penalty. In SC, pages 176-186, 1991.
-
(1991)
SC
, pp. 176-186
-
-
Baer, J.-L.1
Chen, T.-F.2
-
3
-
-
0347781804
-
A discussion on non-blocking/lockup-free caches
-
S. Belayneh and D. R. Kaeli. A discussion on non-blocking/lockup-free caches. SIGARCH Comput. Archit. News, 24(3): 18-25, 1996.
-
(1996)
SIGARCH Comput. Archit. News
, vol.24
, Issue.3
, pp. 18-25
-
-
Belayneh, S.1
Kaeli, D.R.2
-
4
-
-
33646346832
-
The Microarchitecture of the Intel® Pentium® 4 Processor on 90nm Technology
-
D. Boggs, A. Baktha, J. Hawkins, D. T. Marr, J. A. Miller, P. Roussel, R. Singhal, B. Toll, and K. Venkatraman. The Microarchitecture of the Intel® Pentium® 4 Processor on 90nm Technology. Intel® Technology Journal, 8(1), 2004.
-
(2004)
Intel® Technology Journal
, vol.8
, Issue.1
-
-
Boggs, D.1
Baktha, A.2
Hawkins, J.3
Marr, D.T.4
Miller, J.A.5
Roussel, P.6
Singhal, R.7
Toll, B.8
Venkatraman, K.9
-
5
-
-
66749176739
-
-
D. Burger and T. M. Austin. The SimpleScalar Tool Set, Version 2.0. SIGARCH Computer Architecture News, 25(3):13-25, 1997
-
D. Burger and T. M. Austin. The SimpleScalar Tool Set, Version 2.0. SIGARCH Computer Architecture News, 25(3):13-25, 1997.
-
-
-
-
8
-
-
0016059884
-
On Optimization of Memory Hierarchies
-
C. K. Chow. On Optimization of Memory Hierarchies. IBM J. Res. Dev., (2):194-203, 1974.
-
(1974)
IBM J. Res. Dev
, vol.2
, pp. 194-203
-
-
Chow, C.K.1
-
9
-
-
84988438049
-
Toward Kilo-instruction Processors
-
A. Cristal, O. Santana, M. Valero, and J. F. Martínez. Toward Kilo-instruction Processors. ACM TACO, 1(4):389-417, 2004.
-
(2004)
ACM TACO
, vol.1
, Issue.4
, pp. 389-417
-
-
Cristal, A.1
Santana, O.2
Valero, M.3
Martínez, J.F.4
-
10
-
-
0036470119
-
Asim: A Performance Model Framework
-
J. Emer, P. Ahuja, E. Borch, A. Klauser, C.-K. Luk, S. Manne, S. S. Mukherjee, H. Patil, S. Wallace, N. Binkert, R. Espasa, and T. Juan. Asim: A Performance Model Framework. IEEE Computer, 35(2):68-76, 2002.
-
(2002)
IEEE Computer
, vol.35
, Issue.2
, pp. 68-76
-
-
Emer, J.1
Ahuja, P.2
Borch, E.3
Klauser, A.4
Luk, C.-K.5
Manne, S.6
Mukherjee, S.S.7
Patil, H.8
Wallace, S.9
Binkert, N.10
Espasa, R.11
Juan, T.12
-
12
-
-
34249813667
-
A Performance Counter Architecture for Computing Accurate CPI Components
-
S. Eyerman, L. Eeckhout, T. S. Karkhanis, and J. E. Smith. A Performance Counter Architecture for Computing Accurate CPI Components. In ASPLOS-XII, pages 175-184, 2006.
-
(2006)
ASPLOS-XII
, pp. 175-184
-
-
Eyerman, S.1
Eeckhout, L.2
Karkhanis, T.S.3
Smith, J.E.4
-
13
-
-
0012478978
-
How useful are non-blocking loads, stream buffers and speculative execution in multiple issue processors?
-
K. I. Farkas, N. P. Jouppi, and P. Chow. How useful are non-blocking loads, stream buffers and speculative execution in multiple issue processors? In HPCA-1, page 78, 1995.
-
(1995)
HPCA-1
, pp. 78
-
-
Farkas, K.I.1
Jouppi, N.P.2
Chow, P.3
-
14
-
-
0007096183
-
Buffer Block Prefetching Method
-
J. D. Gindele. Buffer Block Prefetching Method. IBM Technical Disclosure Bulletin, 20(2):696-697, 1977.
-
(1977)
IBM Technical Disclosure Bulletin
, vol.20
, Issue.2
, pp. 696-697
-
-
Gindele, J.D.1
-
15
-
-
0003278283
-
The Microarchitecture of the Pentium® 4 Processor
-
G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker, and P. Roussel. The Microarchitecture of the Pentium® 4 Processor. Intel® Technology Journal, 5(1), 2001.
-
(2001)
Intel® Technology Journal
, vol.5
, Issue.1
-
-
Hinton, G.1
Sager, D.2
Upton, M.3
Boggs, D.4
Carmean, D.5
Kyker, A.6
Roussel, P.7
-
16
-
-
0030262662
-
An Analytical Model for Designing Memory Hierarchies
-
B. L. Jacob, P. M. Chen, S. R. Silverman, and T. N. Mudge. An Analytical Model for Designing Memory Hierarchies. IEEE Trans. Computer, 45(10):1180-1194, 1996.
-
(1996)
IEEE Trans. Computer
, vol.45
, Issue.10
, pp. 1180-1194
-
-
Jacob, B.L.1
Chen, P.M.2
Silverman, S.R.3
Mudge, T.N.4
-
17
-
-
0025429331
-
Improving Direct-mapped Cache Performance by the Addition of a Small Fully-associative Cache and Prefetch Buffers
-
N. P. Jouppi. Improving Direct-mapped Cache Performance by the Addition of a Small Fully-associative Cache and Prefetch Buffers. In ISCA-17, pages 364-373, 1990.
-
(1990)
ISCA-17
, pp. 364-373
-
-
Jouppi, N.P.1
-
20
-
-
35348870650
-
Automated Design of Application Specific Superscalar Processors: An Analytical Approach
-
T. S. Karkhanis and J. E. Smith. Automated Design of Application Specific Superscalar Processors: An Analytical Approach. In ISCA-34, pages 402-411, 2007.
-
(2007)
ISCA-34
, pp. 402-411
-
-
Karkhanis, T.S.1
Smith, J.E.2
-
21
-
-
0019892368
-
Lockup-free Instruction Fetch/Prefetch Cache Organization
-
D. Kroft. Lockup-free Instruction Fetch/Prefetch Cache Organization. In ISCA-8, pages 81-87, 1981.
-
(1981)
ISCA-8
, pp. 81-87
-
-
Kroft, D.1
-
22
-
-
66749123601
-
-
Personal Communication. Sept
-
Lieven Eeckhout. Personal Communication. Sept, 2008.
-
(2008)
-
-
Eeckhout, L.1
-
23
-
-
0016482951
-
Storage Hierarchy Optimization Procedure
-
J. E. MacDonald and K. L. Sigworth. Storage Hierarchy Optimization Procedure. IBM J. Res. Dev., 19(2):133-140, 1975.
-
(1975)
IBM J. Res. Dev
, vol.19
, Issue.2
, pp. 133-140
-
-
MacDonald, J.E.1
Sigworth, K.L.2
-
24
-
-
0033365427
-
Exploring Instruction-Fetch Bandwidth Requirement in Wide-issue Superscalar Processors
-
P. Michaud, A. Seznec, and S. Jourdan. Exploring Instruction-Fetch Bandwidth Requirement in Wide-issue Superscalar Processors. In PACT, pages 2-10, 1999.
-
(1999)
PACT
, pp. 2-10
-
-
Michaud, P.1
Seznec, A.2
Jourdan, S.3
-
25
-
-
0038026458
-
An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors
-
P. Michaud, A. Seznec, and S. Jourdan. An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors. Int'l Journal of Parallel Programming, 29(1):35-38, 2001.
-
(2001)
Int'l Journal of Parallel Programming
, vol.29
, Issue.1
, pp. 35-38
-
-
Michaud, P.1
Seznec, A.2
Jourdan, S.3
-
26
-
-
0028767985
-
Theoretical Modeling of Superscalar Processor Performance
-
D. B. Noonburg and J. P. Shen. Theoretical Modeling of Superscalar Processor Performance. In MICRO-27, pages 52-62, 1994.
-
(1994)
MICRO-27
, pp. 52-62
-
-
Noonburg, D.B.1
Shen, J.P.2
-
27
-
-
0030737120
-
A Framework for Statistical Modeling of Superscalar Processor Performance
-
D. B. Noonburg and J. P. Shen. A Framework for Statistical Modeling of Superscalar Processor Performance. In HPCA-3, pages 298-309, 1997.
-
(1997)
HPCA-3
, pp. 298-309
-
-
Noonburg, D.B.1
Shen, J.P.2
-
29
-
-
0036953769
-
Automatically Characterizing Large Scale Program Behavior
-
T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically Characterizing Large Scale Program Behavior. In ASPLOS-X, pages 45-57, 2002.
-
(2002)
ASPLOS-X
, pp. 45-57
-
-
Sherwood, T.1
Perelman, E.2
Hamerly, G.3
Calder, B.4
-
30
-
-
0020177251
-
Cache Memories
-
A. J. Smith. Cache Memories. ACM Computing Surveys, 14(3):473-530, 1982.
-
(1982)
ACM Computing Surveys
, vol.14
, Issue.3
, pp. 473-530
-
-
Smith, A.J.1
-
31
-
-
84874357350
-
-
Standard Performance Evaluation Corporation
-
Standard Performance Evaluation Corporation. SPEC CPU2000 benchmarks. http://www.spec.org.
-
SPEC CPU2000 benchmarks
-
-
-
32
-
-
66749129713
-
-
Personal Communication. Sept
-
Tejas S. Karkhanis. Personal Communication. Sept., 2008.
-
(2008)
-
-
Karkhanis, T.S.1
-
33
-
-
40349098914
-
Scalable Cache Miss Handling for High Memory-Level Parallelism
-
J. Tuck, L. Ceze, and J. Torrellas. Scalable Cache Miss Handling for High Memory-Level Parallelism. In MICRO-39, pages 409-422, 2006.
-
(2006)
MICRO-39
, pp. 409-422
-
-
Tuck, J.1
Ceze, L.2
Torrellas, J.3
-
34
-
-
84983179859
-
Microarchitectural Exploration with Liberty
-
M. Vachharajani, N. Vachharajani, D. A. Penry, J. A. Blome, and D. I. August. Microarchitectural Exploration with Liberty. In MICRO-35, pages 271-282, 2002.
-
(2002)
MICRO-35
, pp. 271-282
-
-
Vachharajani, M.1
Vachharajani, N.2
Penry, D.A.3
Blome, J.A.4
August, D.I.5
-
35
-
-
0038346244
-
SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling
-
R. E. Wunderlich, T. F. Wenisch, B. Falsafi, and J. C. Hoe. SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling. In ISCA-30, pages 84-97, 2003.
-
(2003)
ISCA-30
, pp. 84-97
-
-
Wunderlich, R.E.1
Wenisch, T.F.2
Falsafi, B.3
Hoe, J.C.4
-
36
-
-
33947433665
-
The Future of Simulation: A Field of Dreams
-
J. J. Yi, L. Eeckhout, D. J. Lilja, B. Calder, L. K. John, and J. E. Smith. The Future of Simulation: A Field of Dreams. Computer, 39(11):22-29, 2006.
-
(2006)
Computer
, vol.39
, Issue.11
, pp. 22-29
-
-
Yi, J.J.1
Eeckhout, L.2
Lilja, D.J.3
Calder, B.4
John, L.K.5
Smith, J.E.6
-
37
-
-
0012525243
-
Benchmark health considered harmful
-
C. B. Zilles. Benchmark health considered harmful. SIGARCH Comput. Archit. News, 29(3):4-5, 2001.
-
(2001)
SIGARCH Comput. Archit. News
, vol.29
, Issue.3
, pp. 4-5
-
-
Zilles, C.B.1
|