Parallel simulation of chip-multiprocessor architectures

ACM Transactions on Modeling and Computer Simulation

Volumn 12, Issue 3, 2002, Pages 176-200

  Chidester, Matthew ^a   George, Alan ^b,c  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF FLORIDA   (United States)

^c University of Florida   (United States)

Author keywords

Chip multiprocessors (CMP); Microbenchmarks; Myrinet; Scalable Coherent Interface (SCI)

Indexed keywords

BARRIER TECHNIQUES; CHIP-MULTIPROCESSORS (CMP); MICROBENCHMARK-BASED PASSING INTERFERENCE (MPI); SCALABLE COHERENT INTERFACES (SCI);

CACHE MEMORY; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COUPLED CIRCUITS; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; PARALLEL ALGORITHMS; SYNCHRONIZATION;

MULTIPROCESSING SYSTEMS;

EID: 4243073044     PISSN: 10493301     EISSN: None     Source Type: Journal    
DOI: 10.1145/643114.643116     Document Type: Article

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