Considering all starting points for simultaneous multithreading simulation

ISPASS 2006: IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Volumn 2006, Issue , 2006, Pages 143-153

  Van Biesbrouck, Michael ^a   Eeckhout, Lieven ^b   Calder, Brad ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b GHENT UNIVERSITY   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COMPUTER SYSTEMS PROGRAMMING; OPTIMIZATION;

SIMULTANEOUS MULTITHREADING (SMT);

MULTIPROGRAMMING;

EID: 33750811913     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. A. R. Alameldeen and D. A. Wood. Variability in architectural simulations of multi-threaded commercial workloads. In. Annual International Symposium on High Performance Computer Architecture (HPCA-9), 2003.
2. N. L. Binkert, E. G. Hallnor, and S. K. Reinhardt. Network-oriented full-system simulation using M5. In Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), Feb. 2003.
3. D. C. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. Technical Report CS-TR-97-1342, University of Wisconsin, Madison, June 1997.
4. T. M. Conte, M. A. Hirsch, and K. N. Menezes. Reducing state loss for effective trace sampling of superscalar processors. In Proceedings of the 1996 International Conference on Computer Design (ICCD), Oct. 1996.
5. L. Eeckhout, H. Vandierendonck, and K. De Bosschere. Workload design: Selecting representative program-input pairs. In Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT-2002), pages 83-94, Sept. 2002.
6. M. Ekman and P. Stenström. Enhancing multiprocessor architecture simulation speed using matched-pair comparison. In Proceedings of the 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 89-99, Mar. 2005.
7. G. Hamerly, E. Perelman, J. Lau, and B. Calder. Simpoint 3.0: Faster and more flexible program analysis. In Workshop on Modeling, Benchmarking and Simulation, June 2005.
8. J. L. Kihm, T. Moseley, and D. A. Connors. A mathematical model for accurately balancing co-phase effects in simulated multithreaded systems. In Workshop on Modeling, Benchmarking and Simulation (MoBS) held in conjunction with ISCA, June 2005.
9. T. Lafage and A. Seznec. Choosing representative slices of program execution for microarchitecture simulations: A preliminary application to the data stream. In Workload Characterization of Emerging Applications, Kluwer Academic Publishers, Sept. 2000.
10. J. Lau, J. Sampson, E. Perelman, G. Hamerly, and B. Calder. The strong correlation between code signatures and performance. In IEEE International Symposium on Performance Analysis of Systems and Software, Mar. 2005.
11. E. Perelman, G. Hamerly, and B. Calder. Picking statistically valid and early simulation points. In PACT'03, pages 244-256, Sept. 2003.
12. S. E. Raasch and S.K. Reinhardt. The impact of resource partitioning on SMT processors. In International Conference on Parallel Architectures and Compilation Techniques (PACT), Sept. 2003.
13. T. Sherwood, E. Perelman, and B. Calder. Basic block distribution analysis to find periodic behavior and simulation points in applications. In International Conference on Parallel Architectures and Compilation Techniques, Sept. 2001.
14. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In 10th International Conference on Architectural Support for Programming, Oct. 2002.
15. K. Skadron, P. Ahuja, M. Martonosi, and D. Clark. Branch prediction, instruction-window size, and cache size: Performance tradeoffs and simulation techniques. IEEE Transactions on Computers, 48(11): 1260-81, Nov. 1999.
16. D. M. Tullsen, S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, and R. L. Stamm. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In ISCA, pages 191-202, 1996.
17. M. Van Biesbrouck, L. Eeckhout, and B. Calder. Efficient sampling startup for sampled processor simulation. In 2005 International Conference on High Performance Embedded Architectures and Compilation (HiPEAC), pages 47-67, Nov. 2005.
18. M. Van Biesbrouck, T. Sherwood, and B. Calder. A co-phase matrix to guide simultaneous multithreading simulation. In Proceedings of the 2004 IEEE International Symposium on Performanc e Analysis of Systems and Software (ISPASS'04), Mar. 2004.
19. R. E. Wunderlich, T. F. Wenisch, B. Falsafi, and J. C. Hoe. Smarts: Accelerating microarchitecture simulation via rigorous statistical sampling. In 30th International Symposium on Computer Architecture, June 2003.