Construction and use of linear regression models for processor performance analysis

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 2006, Issue , 2006, Pages 99-108

  Joseph, P J ^a   Vaswani, Kapil ^a   Thazhuthaveetil, Matthew J ^a  

^a INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ERROR CORRECTION; ITERATIVE METHODS; REGRESSION ANALYSIS;

LINEAR REGRESSION MODELS; MICRO-ARCHITECTURAL PARAMETERS; SUPERSCALAR PROCESSOR SIMULATORS;

PROGRAM PROCESSORS;

EID: 33748863916     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2006.1598116     Document Type: Conference Paper

References (13)

1. R. Desikan, D. Burger, and S. W. Keckler. Measuring Experimental Error in Microprocessor Simulation. In Proceedings of 28th Annual International Symposium on Computer Architecture, July 2001.
2. P. G. Emma. Understanding Some Simple Processor-Performance Limits. IBM Journal of Research and Development, 41(3), 1997.
3. B. A. Fields, R. Bodik, M. D. Hill, and C. J. Newburn. Using Interaction Costs for Microarchitectural Bottleneck Analysis. In Proceedings of the 36th International Symposium on Microarchitecture, December 2003.
4. C. M Hurvich and C-L Tsai. Regression and Time Series Model Selection in Small Samples. Biometrika, 76:297-307, 1989.
5. P. J. Joseph, K. Vaswani, and M. J. Thazhuthaveetil. Construction and Use of Linear Regression Models for Processor Performance Analysis. Technical Report IISc-CSA-TR-2005-16, Department of Computer Science & Automation, Indian Institute of Science, November 2005.
6. T. Karkhanis and J. E. Smith. A First-order Model of Superscalar Processors. In Proceedings of the 31st Annual International Symposium on Computer Architecture, June 2004.
7. A. J. KleinOsowski and D. J. Lilja. MinneSPEC: A new SPEC Benchmark Workload for Simulation-Based Computer Architecture Research. Computer Architecture Letters, June 2002.
8. D.C.Montgomery. Design and Analysis of Experiments. Wiley, 5th edition, 2001.
9. D. B. Noonburg and J. P. Shen. Theoretical Modeling of Superscalar Processor Performance. In Proceedings of the 27th International Symposium on Microarchitecture, December 1994.
10. E. Rotenberg, S. Bennett, and J. E. Smith. Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. In Proceedings of the 29th International Symposium on Microarchitecture, December 1996.
11. Y. Sakamoto, M. Ishiguro, and G. Kitagawa. Akaike Information Criterion Statistics. Kluwer Academic Publishers, 1987.
12. J. J. Yi, D. J. Lilja, and D. M. Hawkins. A Statistically Rigorous Approach for Improving Simulation Methodology. In Proceedings of the 9th International Symposium on High Performance Computer Architecture, February 2003.
13. J. J. Yi, D. J. Lilja, R. Sendag, S. V. Kodakara, and D. M. Hawkins. Characterizing and Comparing Prevailing Simulation Techniques. In Proceedings of the 11th International Symposium on High Performance Computer Architecture, January 2005.