MisSPECulation: Partial and misleading use of SPEC CPU2000 in computer architecture conferences

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2003, Pages 52-59

  Citron, Daniel ^a  

^a IBM HAIFA RESEARCH LAB   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER SIMULATION; PROGRAM COMPILERS; RESPONSE TIME (COMPUTER SYSTEMS); STANDARDS; TECHNICAL PRESENTATIONS;

CENTRAL PROCESSING UNIT; DATA CACHE;

COMPUTER ARCHITECTURE;

EID: 0038008203     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. J. F. Cantin and M. D. Hill, "Cache Performance for SPEC CPU2000 Benchmarks", http://www.cs.wisc.edu/multifacet/misc/spec2000cachedata.
2. D. Citron, D. Feitelson and L. Rudolph, "Accelerating Multi-Media Processing by Implementing Memoing in Multiplication and Division Units", Proc. of the 8th Int. Conf. on Architectural Support for Programming Languages and Operating Systems, pp. 252-261, October 1998.
3. R. Giladi and N. Ahituv, "SPEC as a Performance Evaluation Measure", Computer 28:8, pp. 33-44, August 1995.
4. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 3rd edition, Morgan Kaufmann Publishers, 2003.
5. AJ KleinOsowski and D. J. Lilja, "MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research", Computer Architecture Letters, June 2002.
6. T. Lafage and A. Seznec, "Choosing Representative Slices of Program Execution for Microarchitecture Simulations: A Preliminary Application to the Data Stream", in IEEE 3rd Annual Workshop on Workload Characterization (WWC-2000) held in Cojunction with the International Conference on Computer Design (ICCD-2000), September 2000.
7. M. Moudgill, J. Wellman, and J. Moreno, "Environment for PowerPC Microarchitecture Exploration", IEEE Micro 19(3), pp. 15-25, May/June 1999.
8. S. Nussbaum and J. E. Smith, "Modeling Superscalar Processors via Statistical Simulation", in Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT-2001), pp. 15-24, September 2001.
9. D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M.R. Stan, "Power Issues Related to Branch Prediction", Proc. of the 8th Int. Symp. on High-Performance Computer Architecture, pp. 233-244, February 2002.
10. SimpleScalar LLC, http://www.simplescalar.com.
11. Smith J.E., "Characterizing Computer Performance With a Single Number", Comm. ACM 31:10, pp. 1202-1206, October 1988.
12. Standard Performance Evaluation Corporation, CPU2000, http://www/spec.org/osg/cpu2000.
13. Standard Performance Evaluation Corporation, CPU95, http://www.spec.org/osg/cpu95.
14. SPEC CPU Benchmark Search Program, http://www.spec.org/cpu2000/CPU2004.