SlackSim: A platform for parallel simulations of CMPs on CMPs

Performance Evaluation Review

Volumn 37, Issue 2, 2009, Pages 77-78

  Chen, Jianwei ^a   Annavaram, Murali ^a   Dubois, Michel ^a  

^a University of Southern California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED MEMORY MACHINES; FEW-CYCLE; HARDWARE THREADS; INHERENT PARALLELISM; MICRO ARCHITECTURES; MULTIPROCESSOR SIMULATION; PARALLEL SIMULATIONS; PTHREADS; SIMULATION ERROR; SIMULATION FRAMEWORK; SIMULATION PARADIGM;

COMPUTER SIMULATION;

EID: 77958075524     PISSN: 01635999     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1639562.1639594     Document Type: Conference Paper

References (7)

1. T. Austin, E. Larson and D. Ernst, "SimpleScalar: An Infrastructure for Computer System Modeling", IEEE Computer, Feb. 2002, pp. 59-67.
2. J. Chen, M. Annavaram, and M. Dubois, "SlackSim: A Platform for Parallel Simulations of CMPs on CMPs", CENG-2008-6, Department of Electrical Engineering, University of Southern California, 2008.
3. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The Splash-2 Programs: Characterization and Methodological Considerations," in Proceedings of the International Symposium on Computer Architecture, pp. 24-36, June 1995.
4. M. Chidester and A. George, "Parallel Simulation of Chip-multiprocessor Architectures," ACM Transactions on Modeling and Computer Simulation, Vol. 12, Issue 3, pp. 176-200, July 2002.
5. R. M. Fujimoto, "Parallel Discrete Event Simulation," Communication of the ACM, Vol 33 No. 10, pp. 30-53, Oct. 1990.
6. N. Manjikian, "Multiprocessor enhancements of the SimpleSca-lar tool set," ACM SIGARCH Computer Architecture News, Vol. 29, Issue 1, pp. 8-15, Mar. 2001.
7. S. S. Mukherjee, S. Reinhardt, B. Falsafi, M. Litzkow, S. Huss-Lederman, M. D. Hill, J. R. Larus, and D. A. Wood, "Wisconsin Wind Tunnel II: A Fast, Portable Parallel Architecture Simulator," IEEE Concurrency, Vol.8 No. 4, pp. 12-20, 2000.