MicroLib: A case for the quantitative comparison of micro-architecture mechanisms

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2004, Pages 43-54

  Pérez, Daniel Gracia ^a   Mouchard, Gilles ^a   Temam, Olivier ^a  

^a INRIA   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK SELECTION; DATA CACHES; MICRO-ARCHITECTURE; MICROLIB;

BENCHMARKING; BUFFER STORAGE; COMPUTER HARDWARE; COMPUTER SIMULATION; ERROR ANALYSIS; MATHEMATICAL MODELS; OPTIMIZATION; PROGRAM PROCESSORS; REVERSE ENGINEERING;

COMPUTER ARCHITECTURE;

EID: 17644388982     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2004.25     Document Type: Conference Paper

References (30)

1. MicroLib. http://www.microlib.org.
2. OPENCORES. http://www.opencores.org, 2001-2004.
3. D. Burger and T. Austin. The simplescalar tool set, version 2.0. Technical Report CS-TR-97-1342, Department of Computer Sciences, University of Wisconsin, June 1997.
4. R. Cooksey, S. Jourdan, and D. Grunwald. A stateless, content-directed data prefetching mechanism. In Proceedings of the 10th international conference on architectural support for programming languages and operating systems (ASPLOS-X), pages 279-290, San Jose, California, October 2002.
5. V. Cuppu, B. Jacob, B. Davis, and T. Mudge. A performance comparison of contemporary dram architectures. In Proceedings of the 26th annual international symposium on Computer architecture (ISCA), pages 222-233, Atlanta, Georgia, United States, June 1999.
6. J. Emer, P. Ahuja, E. Borch, A. Klauser, C.-K. Luk, S. Manne, S. S. Mukkerjee, H. Patil, S. Wallace, N. Binkert, and T. Juan. ASIM: A performance model framework. In IEEE Computer, Vol. 35, No. 2, February 2002.
7. J. W. C. Fu, J. H. Patel, and B. L. Janssens. Stride directed prefetching in scalar processors. In Proceedings of the 25th annual international symposium on Microarchitecture, pages 102-110. IEEE Computer Society Press, 1992.
8. C. Green. Analyzing and implementing SDRAM and SGRAM controllers. In EDN (www.edn.com), February 1998.
9. Z. Hu, S. Kaxiras, and M. Martonosi. Timekeeping in the memory system: predicting and optimizing memory behavior. In Proceedings of the 29th annual international symposium on Computer architecture (ISCA), pages 209-220, Anchorage, Alaska, May 2002.
10. Z. Hu, M. Martonosi, and S. Kaxiras. TCP: Tag correlating prefetchers. In Proceedings of the 9th International Symposium on High Performance Computer Architecture (HPCA), Anaheim, California, February 2003.
11. M. Huang, J. Renau, S. M. Yoo, and J. Torrellas. L1 data cache decomposition for energy effi ciency. In International Symposium on Low Power Electronics and Design (ISLPED 01), Huntington Beach, California, August 2001.
12. D. Joseph and D. Grunwald. Prefetching using markov predictors. In Proceedings of the 24th annual international symposium on Computer architecture (ISCA), pages 252-263, Denver, Colorado, United States, June 1997.
13. N. P. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. Technical report, Digital, Western Research Laboratory, Palo Alto, March 1990.
14. A.-C. Lai, C. Fide, and B. Falsafi. Dead-block prediction & dead-block correlating prefetchers. In Proceedings of the 28th annual international symposium on Computer architecture (ISCA), pages 144-154, Gteborg, Sweden, June 2001.
15. H.-H. S. Lee, G. S. Tyson, and M. K. Farrens. Eager writeback - a technique for improving bandwidth utilization. In Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, pages 11-21. ACM Press, 2000.
16. G. Mouchard. PowerPC G3 simulator. http://www.microlib.org/G3/PowerPC750. php, 2002.
17. K. J. Nesbit and J. E. Smith. Data cache prefetching using a global history buffer. In Proceedings of the 10th International Symposium on High Performance Computer Architecture (HPCA), page 96, Madrid, Spain, February 2004.
18. OSCI. SystemC. http://www.systemc.org, 2000-2004.
19. R. Rakvic, B. Black, D. Limaye, and J. P. Shen. Non-vital loads. In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture. ACM Press, 2002.
20. T. Rockicki. Indexing memory banks to maximize page mode hit percentage and minimize memory latency. Technical report, HP Laboratories Palo Alto, June 1996.
21. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In Tenth international conference on architectural support for programming languages and operating systems on Proceedings of the 10th international conference on architectural support for programming languages and operating systems (ASPLOS-X), pages 45-57. ACM Press, 2002.
22. P. Shivakumar and N. P. Jouppi. CACTI 3.0: An integrated cache timing, power and area model. Technical report, HP Laboratories Palo Alto, August 2001.
23. A. J. Smith. Cache memories. Computing Surveys, 14(3):473-530, September 1982.
24. SPEC. SPEC2000. http://www.spec.org.
25. M. Vachharajani, N. Vachharajani, D. A. Penry, J. A. Blome, and D. I. August. Microarchitectural exploration with Liberty. In Proceedings of the 35th International Symposium on Microarchitecture (MICRO), Istanbul, Turkey, November 2002.
26. R. E. Wunderlich, T. F. Wenisch, B. Falsafi, and J. C. Hoe. Smarts: accelerating microarchitecture simulation via rigorous statistical sampling. In Proceedings of the 30th annual international symposium on Computer architecture, pages 84-97. ACM Press, 2003.
27. J. Yang and R. Gupta. Energy efficient frequent value data cache design. In Proceedings of the 35th international symposium on Microarchitecture (MICRO), pages 197-207, Istanbul, Turkey, November 2002.
28. Y. Zhang and R. Gupta. Enabling partial cache line prefetching through data compression. In International Conference on Parallel Processing (ICPP), Kaohsiung, Taiwan, October 2003.
29. Y. Zhang, J. Yang, and R. Gupta. Frequent value locality and value-centric data cache design. In Proceedings of the 9th international conference on Architectural support for programming languages and operating systems (ASPLOS-IX), pages 150-159, Cambridge, Massachusetts, United States, November 2000.
30. Z. Zhang, Z. Zhu, and X. Zhang. A permutation-based page interleaving scheme to reduce row-buffer conficts and exploit data locality. In Proceedings of the 33rd international symposium on Microarchitecture (MICRO), Monterey, California, December 2000.