Exploiting parallelism and structure to accelerate the simulation of chip multi-processors

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 2006, Issue , 2006, Pages 27-38

  Penry, David A ^a   Fay, Daniel ^b   Hodgdon, David ^b   Wells, Ryan ^a   Schelle, Graham ^b   August, David I ^a   Connors, Dan ^b  

^a Princeton University   (United States)

^b UCB 450   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATED SIMULATOR PARALLELIZATION; HARDWARE INTEGRATION; INTEGRATING MULTIPLE PROCESSORS; REPARTITIONING;

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; MULTIPROCESSING SYSTEMS; PERSONAL COMPUTERS; PROGRAM PROCESSORS;

MICROPROCESSOR CHIPS;

EID: 33748872867     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2006.1598110     Document Type: Conference Paper

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