System-level performance metrics for multiprogram workloads

IEEE Micro

Volumn 28, Issue 3, 2008, Pages 42-53

  Eyerman, Stijn ^a   Eeckhout, Lieven ^a  

^a GHENT UNIVERSITY   (Belgium)

Author keywords

Fairness; Multiprogram workloads; Normalized turnaround time; Performance metrics; System throughput

Indexed keywords

TURNAROUND TIME;

BALANCE (WEIGHTING); MULTI-THREADED; PERFORMANCE METRICS; PROGRAM PERFORMANCE; SYSTEM LEVELS; SYSTEM PERFORMANCES; SYSTEM THROUGHPUT; SYSTEM-LEVEL PERFORMANCE; TOP-DOWN; USER-ORIENTED;

MILITARY OPERATIONS;

EID: 47249094055     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2008.44     Document Type: Article

References (20)

1. J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, 3rd ed., Morgan Kaufmann, 2003.
2. A.R. Alameldeen and D.A. Wood, "IPC Considered Harmful for Multiprocessor Workloads," IEEE Micro, vol. 26, no. 4, July/Aug. 2006, pp. 8-17.
3. A. Snavely and D.M. Tullsen, "Symbiotic Job Scheduling for Simultaneous Multi threading Processor," Proc. 9th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 00), ACM Press, 2000, pp. 234-244.
4. K. Luo, J. Gummaraju, and M. Franklin, "Balancing Throughput and Fairness in SMT Processors," Proc. IEEE Int'l Symp. Performance Analysis of Systems and Software (ISPASS 01), IEEE Press, 2001, pp. 164-171.
5. W. Stallings, Operating Systems: Internals and Design Principles, 5th ed., Prentice Hall, 2005.
6. L.K. John, "Aggregating Performance Metrics over a Benchmark Suite," Performance Evaluation and Benchmarking, L.K. John and L. Eeckhout, eds., (2006), CRC Press, 2006, pp. 47-58.
7. T. Sherwood et al., "Automatically Characterizing Large Scale Program Behavior," Proc. 10th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 02), ACM Press, 2002, pp. 45-57.
8. M. Van Biesbrouck, T. Sherwood, and B. Calder, "A Co-Phase Matrix to Guide Simultaneous Multithreading Simulation," Proc. Int'l Symp. Performance Analysis of Systems and Software (ISPASS), IEEE CS Press, 2004, pp. 45-56.
9. N. Tuck and D.M. Tullsen, "Initial Observations of the Simultaneous Multithreading Pentium 4 Processor," Proc. 12th Int'l Conf. Parallel Architectures and Compilation Techniques (PACT 03), IEEE CS Press, 2003, pp. 26-34.
10. T.M. Conte, M.A. Hirsch, and K.N. Menezes, "Reducing State Loss for Effective Trace Sampling of Superscalar Processors," Proc. Int'l Conf. Computer Design (ICCD 96), IEEE CS Press, 1996, pp. 468-477.
11. R.E. Wunderlich et al., "SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling," Proc. 30th Ann. Int'l Symp. Computer Architecture (ISCA 03), IEEE CS Press, 2003, pp. 84-95.
12. J.J. Yi et al., "Characterizing and Comparing Prevailing Simulation Techniques," Proc. 11th Int'l Symp. High-Performance Computer Architecture (HPCA 05), IEEE CS Press, 2005, pp. 266-277.
13. J. Vera et al., "FAME: Fairly Measuring Multithreaded Architectures," Proc. 16th Int'l Conf. Parallel Architectures and Compilation Techniques (PACT 07), IEEE CS Press, 2007, pp. 305-316.
14. M. Van Biesbrouck, L. Eeckhout, and B. Calder, "Representative Multiprogram Workloads for Multithreaded Processor Simulation," Proc. IEEE 10th Int'l Symp. Workload Characterization (IISWC 07), 2007, pp. 193-203.
15. F.J. Cazorla et al., "Predictable Performance in SMT Processors: Synergy between the OS and SMTs," IEEE Trans. Computers, vol. 55, no. 7, July 2006, pp. 785-799.
16. R. Gabor, S. Weiss, and A. Mendelson, "Fairness Enforcement in Switch-On Event Multithreading," ACM Trans. Architecture and Code Optimization, vol. 4, no. 3, Sept. 2007.
17. D.M. Tullsen et al., "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor," Proc. 23rd Ann. Int'l Symp. Computer Architecture (ISCA 96), IEEE CS Press, 1996, pp. 191-202.
18. D.M. Tullsen and J.A. Brown, "Handling Long-Latency Loads in a Simultaneous Multithreading Processor," Proc. 34th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO 01), IEEE CS Press, 2001, pp. 318-327.
19. F.J. Cazorla et al., "Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors," Int'l J. High Performance Computing and Networking, vol. 2, no. 1, 2004, pp. 45-54.
20. S. Eyerman and L. Eeckhout, "A Memory-Level Parallelism Aware Fetch Policy for SMT Processors," Proc. 13th Int'l Symp. High-Performance Computer Architecture (HPCA 07), IEEE CS Press, 2007, pp. 240-249.