Improving the accuracy vs. speed tradeoff for simulating shared-memory multiprocessors with ILP processors

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 1999, Pages 23-32

  Durbhakula, Murthy ^a   Pai, Vijay S ^a   Adve, Sarita ^a  

^a RICE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER SELECTION AND EVALUATION; COMPUTER SIMULATION; ERROR ANALYSIS; PARALLEL PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); STORAGE ALLOCATION (COMPUTER);

INSTRUCTION-LEVEL PARALLELISM (ILP); SHARED-MEMORY MULTIPROCESSORS; SOFTWARE PACKAGE DIRECTRSIM;

COMPUTER ARCHITECTURE;

EID: 0032805141     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/hpca.1999.744317     Document Type: Conference Paper

References (13)