An analytical model for a gpu architecture with memory-level and thread-level parallelism awareness

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2009, Pages 152-163

  Hong, Sunpyo ^a   Kim, Hyesoon ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Georgia Institute of Technology   (United States)

Author keywords

Analytical model; CUDA; GPU architecture; Memory level parallelism; Performance estimation; Warp level parallelism

Indexed keywords

ABSOLUTE ERROR; ANALYTICAL MODEL; APPLICATION PERFORMANCE; DEGREE OF MEMORY; DESIGN SPACES; EXECUTION TIME; GEOMETRIC MEAN; GPU COMPUTING; KEY COMPONENT; MEMORY BANDWIDTHS; MEMORY LEVEL PARALLELISMS; MODEL ESTIMATES; MULTI CORE; OVERALL EXECUTION; PARALLEL APPLICATION; PARALLEL MEMORY; PARALLEL PROCESSOR; PARALLEL PROGRAM; PERFORMANCE BOTTLENECKS; PERFORMANCE CHARACTERISTICS; PERFORMANCE ESTIMATION; PROGRAMMING LANGUAGE; SOFTWARE ENGINEERS; THREAD LEVEL PARALLELISM;

COMPUTER GRAPHICS EQUIPMENT; COMPUTER SIMULATION; COMPUTERS; ESTIMATION; MICROPROCESSOR CHIPS; MODELS; PARALLEL ARCHITECTURES; PROGRAM PROCESSORS; QUERY LANGUAGES; WEAVING;

BENCHMARKING;

EID: 70450231944     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1555754.1555775     Document Type: Conference Paper

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