메뉴 건너뛰기




Volumn 2006, Issue , 2006, Pages 2-12

Simulation sampling with live-points

Author keywords

[No Author keywords available]

Indexed keywords

FUNCTIONAL SIMULATION; MICROARCHITECTURAL CONFIGURATION; SIMULATION SAMPLING; SUPERSCALAR PROCESSORS;

EID: 33750832560     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (43)

References (38)
  • 2
    • 0003465202 scopus 로고    scopus 로고
    • Technical Report 1342, Computer Sciences Department, University of Wisconsin-Madison, June
    • D. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. Technical Report 1342, Computer Sciences Department, University of Wisconsin-Madison, June 1997.
    • (1997) The SimpleScalar Tool Set, Version 2.0.
    • Burger, D.1    Austin, T.M.2
  • 13
    • 0034226001 scopus 로고    scopus 로고
    • SPEC CPU2000: Measuring CPU performance in the new millennium
    • J. L. Henning. SPEC CPU2000: Measuring CPU performance in the new millennium. Computer, 33(7):28-35, 2000.
    • (2000) Computer , vol.33 , Issue.7 , pp. 28-35
    • Henning, J.L.1
  • 14
    • 0024903997 scopus 로고
    • Evaluating associativity in cpu caches
    • Dec.
    • M. D. Hill and A. J. Smith. Evaluating associativity in cpu caches. IEEE Transactions on Computers, C-38(12): 1612-1630, Dec. 1989.
    • (1989) IEEE Transactions on Computers , vol.C-38 , Issue.12 , pp. 1612-1630
    • Hill, M.D.1    Smith, A.J.2
  • 18
    • 0028445155 scopus 로고
    • A comparison of trace-sampling techniques for multi-megabyte caches
    • June
    • R. E. Kessler, M. D. Hill, and D. A. Wood. A comparison of trace-sampling techniques for multi-megabyte caches. IEEE Transactions on Computers, 43(6):664-675, June 1994.
    • (1994) IEEE Transactions on Computers , vol.43 , Issue.6 , pp. 664-675
    • Kessler, R.E.1    Hill, M.D.2    Wood, D.A.3
  • 19
    • 1842849819 scopus 로고    scopus 로고
    • Choosing representative slices of program execution for microarchitecture simulations: A preliminary application to the data stream
    • Sept.
    • T. Lafage and A. Seznec. Choosing representative slices of program execution for microarchitecture simulations: A preliminary application to the data stream. In IEEE Workshop on Workload Characterization, ICCD, Sept. 2000.
    • (2000) IEEE Workshop on Workload Characterization, ICCD
    • Lafage, T.1    Seznec, A.2
  • 20
    • 0024107186 scopus 로고
    • Accurate low-cost methods for performance evaluation of cache memory systems
    • Feb.
    • S. Laha, J. H. Patel, and R. K. Iyer. Accurate low-cost methods for performance evaluation of cache memory systems. IEEE Transactions on Computers, Volume C-37(11): 1325-1336, Feb. 1988.
    • (1988) IEEE Transactions on Computers , vol.C-37 , Issue.11 , pp. 1325-1336
    • Laha, S.1    Patel, J.H.2    Iyer, R.K.3
  • 21
    • 0028135744 scopus 로고
    • Accelerating architectural simulation by parallel execution of trace samples
    • Architecture, Jan.
    • G. Lauterbach. Accelerating architectural simulation by parallel execution of trace samples. In Hawaii International Conference on System Sciences, volume Volume 1: Architecture, pages 205-210, Jan. 1994.
    • (1994) Hawaii International Conference on System Sciences , vol.1 , pp. 205-210
    • Lauterbach, G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.