Quick performance models quickly: Closely-coupled partitioned simulation on FPGAs

ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2008, Pages 1-10

  Pellauer, Michael ^a   Vijayaraghavan, Muralidaran ^a   Adler, Michael ^b   Arvind, ^a   Emer, Joel ^a,b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

FPGAs; Performance modeling; Simulation

Indexed keywords

FINE-GRAINED PARALLELISM; FPGAS; IMPLEMENTATION COMPLEXITY; INTERNATIONAL SYMPOSIUM; MODEL DEVELOPMENT; PERFORMANCE ANALYSES; PERFORMANCE MODELING; PERFORMANCE MODELLING; SIMULATION; SIMULATION SPEED; SYSTEMS-AND-SOFTWARE; TIMING MODELS;

CHLORINE COMPOUNDS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INFORMATION THEORY; TECHNICAL PRESENTATIONS; TIME MEASUREMENT;

COMPUTER SOFTWARE;

EID: 52249085406     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2008.4510733     Document Type: Conference Paper

References (22)

1. Arvind, K. Asanovic, D. Chiou, J. C. Hoe, C. Kozyrakis, S.L. Lu, M. Oskin, D. Patterson, J. Rabaey, and J. Wawrzynek. RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental. Parallel HW/SW Platform. Technical Report.
2. Bluespec, Inc. Bluespec Language Reference Manual.
3. D. Chiou, D. Sunwoo, J. Kim, N. A. Patil, W. H. Reinhart, D. E. Johnson and Z. Xu. The FAST Methodology for High-Speed SoC/Computer Simulation. Proceedings of International Conference on Computer-Aided Design (ICCAD), 2007.
4. D. Chiou, D. Sunwoo, J. Kim, N. Patil, W. Reinhart, D. E. Johnson, J. Keefe and H. Angepat. FPGA-Accelerated Simulation Technologies FAST: Fast, Full-System, Cycle-Accurate Simulators. Proceedings of MICRO, 2007.
5. E. Chung, E. Nurvitadhi, J. Hoe, K. Mai, and B. Falsafi. Accelerating Architectural-level, Full-System Multiprocessor Simulations using FPGAs. In FPGA '08: Proceedings of the 2003 ACM SIGDA Eleventh International Symposium on Field Programmable Gate Arrays, 2008.
6. N. Dave, M. Pellauer, Arvind, and J. Emer. Implementing a Functional/Timing Partitioned Microprocessor Simulator with an FPGA. 2nd Workshop on Architecture Research using FPGA Platforms (WARFP), February 2006.
7. J. Emer, P. Ahuja, E. Borch, A. Klauser, C. K. Luk, S. Manne, S. S. Mukherjee, H. Patil, S. Wallace, N. Binkert, R. Espasa, and T. Juan, Asim: A Performance Model Framework. Computer, vol. 35, no. 2, pp. 68-76, February, 2002.
8. D. Fang, C. LaFrieda, S. Peng, and R. Manohar. A 3-Tier Asynchronous FPGA. In Proceedings of the 23rd International VLSI/ULSI Multilevel Interconnection Conference, September 2006.
9. G. Gibeling, A, Schultz, and K. Asanovic. The RAMP Architecture & Description Language. Technical Report.
10. S.H. Kim, W.H. Tranter, S.F. Midkiff, Middleware for a distributed reconfigurable simulator. In Proceedings of the 35th Annual Simulation Symposium, pp. 253-258, 2002.
11. E. Larson, S. Chatterjee, and T. Austin. MASE: A Novel Infrastructure for Detailed Microarchitectural Modeling. In Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), Nov. 2001.
12. S.L. Lu, P. Yiannacouras, T. Suh, R. Kassa, and M. Konow. An FPGA-Based Pentium(R) in a Complete Desktop System. In Proceedings of the Fifteenth ACM SIGDA International Symposium on Field Programmable Gate Arrays (ISFPGA), February 2007
13. C.J. Mauer, M.D. Hill, and D.A. Wood. Full-System Timing-First Simulation. ACM SIGMETRICS Performance Evaluation Review. Volume 30.1, pp. 108-116, 2002
14. Page, I. Constructing Hardware-Software Systems from a Single Description. In Journal of VLSI Signal Processing, Volume 12, pp. 87-107, 1996.
15. A. Parashar, M. Adler, J. Emer. Facilitating Cross-FPGA Platform Designs using "Virtual" Platforms. The First Bluespec Workshop, August 2007. http://csg.csail.mit.edu/bluespec/
16. M. Pellauer, M. Vijaraghavan, M. Adler, Arvind, and J. Emer. A-Ports: A Distributed, Efficient Abstraction for Performance Models on FPGAs. International Symposium on Field-Programmable Gate Arrays (ISFPGA), 2008.
17. D. A. Penry, D. Fay, D. Hodgdon, R. Wells, G. Schelle, D. I. August and D. Connors. Exploiting Parallelism and Structure to Accelerate the Simulation of Chip Multi-processors. In Proceedings of the 12th International Symposium on High-Performance Computer Architecture (HPCA), February 2006, pp. 27-38.
18. J. Ray and J.C. Hoe. High-Level Modeling and FPGA Prototyping of Microprocessors. In FPGA '03: Proceedings of the 2003 ACM SIGDA Eleventh International Symposium on Field Programmable Gate Arrays, pages 100-107, 2003.
19. L. Soule and A. Gupta. Parallel Distributed-Time Logic Simulation. In IEEE Design and Test, November 1989, pp. 32-48.
20. J. Wawrzynek, D. Patterson, M. Oskin, S. Lu, C. Kozyrakis, J. C. Hoe, D. Chiou, and K. Asanovic. RAMP: A Research Accelerator for Multiple Processors, IEEE Micro Mar/Apr 2007, pp. 46-57.
21. R. Wunderlich and J. C. Hoe. In-System FPGA Prototyping of an Itanium Microarchitecture. In Proceedings of International Conference on Computer Design (ICCD), October 2004.
22. Xilinx Inc. Website, http://www.xilinx.com/