Efficient sampling startup for simpoint

IEEE Micro

Volumn 26, Issue 4, 2006, Pages 32-42

  Van Biesbrouck, Michael ^a   Calder, Brad ^a,c   Eeckhout, Lieven ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b GHENT UNIVERSITY   (Belgium)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33947713690     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2006.68     Document Type: Review

References (9)

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2. T. Sherwood et al., "Automatically Characterizing Large Scale Program Behavior," Proc. 10th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS 02), ACM Press, 2002, pp. 45-57.3. R.E. Wunderlich et al., "SMARTS:
3. Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling," Proc. 30th Int'l Symp. Computer Architecture (ISCA 03), ACM Press, 2003, pp. 84-97.
4. M. Van Biesbrouck, L. Eeckhout, and B. Calder, "Efficient Sampling Startup for Sampled Processor Simulation," Proc. Int'l Conf. High Performance Embedded Architectures and Compilation (HiPEAC 05), Springer, 2005, pp. 47-67.
5. M. Durbhakula, V.S. Pai, and S. Adve, "Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors," Proc. Fifth Int'l Symp. High-Performance Computer Architecture (HPCA 99), IEEE CS Press, 1999, pp. 23-32.
6. J. Ringenberg et al., "Intrinsic Checkpointing: A Methodology for Decreasing Simulation Time through Binary Modification," Proc. IEEE Int'l Symp. Performance Analysis of Systems and Software (ISPASS 05), IEEE, 2005, pp. 78-88.
7. T.W. Wenisch et al., "Simulation Sampling with Live-Points," Proc. IEEE Int'l Symp. Performance Analysis of Systems and Software (ISPASS 06), IEEE, 2006, pp. 2-12.
8. J. Haskins and K. Skadron, "Accelerated Warmup for Sampled Microarchitecture Simulation," ACM Trans. Architecture and Code Optimization, vol. 2, no. 1, Mar. 2005, pp. 78-108.
9. L. Eeckhout et al., "BLRL: Accurate and Efficient Warmup for Sampled Processor Simulation," The Computer J., vol. 48, no. 4, July 2005, pp. 451-459.