DIST: A simple, reliable and scalable method to significantly reduce processor architecture simulation time

Performance Evaluation Review

Volumn 31, Issue 1, 2003, Pages 1-12

  Girbal, Sylvain ^a   Mouchard, Gilles ^a   Cohen, Albert ^b   Temam, Olivier ^a  

^a UNIVERSITÉ PARIS SACLAY   (France)

^b INRIA ROCQUENCOURT   (France)

Author keywords

Distributed simulation; Processor architecture

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DISTRIBUTED COMPUTER SYSTEMS; ERRORS; RELIABILITY; SIMULATORS;

ARCHITECTURE SIMULATION; DISTRIBUTED SIMULATION; PROCESSOR ARCHITECTURE; TRIAL-AND-ERROR RESEARCH PROCESSES;

PROGRAM PROCESSORS;

EID: 33646184191     PISSN: 01635999     EISSN: 01635999     Source Type: Conference Proceeding    
DOI: 10.1145/885651.781029     Document Type: Conference Paper

References (24)

1. J. Anderson, L. Berc, J. Dean, S. Ghemawat, M. Henzinger, S. Leung, D. Sites, M. Vandevoorde, C. Waldspurger, and W. Weihl. Continuous profiling: Where have all the cycles gone, July 1997.
2. P. Bose and T. M. Conte. Performance analysis and its impact on design. IEEE Computer, pages 41-49, May 1998.
3. D. Burger and T. Austin. The simplescalar tool set, version 2.0. Technical Report CS-TR-97-1342, Department of Computer Sciences, University of Wisconsin, June 1997.
4. S. Chatterjee and S. Sen. Cache-efficient matrix transposition. In Sixth International Symposium on High-Performance Computer Architecture, pages 195-205, Toulouse, France, 2000.
5. T. Conte, M. Hirsch, and K. Menezes. Reducing state loss for effective trace sampling of superscalar processors. In International Conference on Computer Design, pages 468-477, 1996.
6. J. Dean, J. E. Hicks, C. A. Waldspurger, W. E. Weihl, and G. Z. Chrysos. ProfileMe: Hardware support for instruction-level profiling on out-of-order processors. In International Symposium on Microarchitecture, pages 292-302, Research Triangle Park, North Carolina, 1997.
7. R. Desikan, D. Burger, and S. W. Keckler. Measuring experimental error in microprocessor simulation. In The 28th Annual Intl. Symposium on Computer Architecture, pages 266-277, June 2001.
8. L. Eeckhout, K. DeBousschere, and H. Neefs. Performance analysis through synthetic trace generation. In Int. Symp. on Performance Analysis of Systems and Software, Liege, Belgium, April 2000.
9. J. Haskins and K. Skadron. Minimal subset evaluation: Rapid warm-up for simulated hardware state. In Proc. of the 2001 International Conference on Computer Design, Austin, Texas, September 2001.
10. V. S. Iyengar and L. H. Trevillyan. Evaluation and generation of reduced traces for benchmarks. Technical Report RC20610, IBM T. J. Watson, Oct 1996.
11. A. KleinOsowski, J. Flynn, N. Meares, and D. Lilja. Adapting the SPEC 2000 benchmark suite for simulation-based computer architecture research. In Proceedings of the Third IEEE Annual Workshop on Workload Characterization, International Conference on Computer Design (ICCD), pages 73-82, September 2000.
12. T. Lafage, A. Seznec, E. Rohou, and F. Bodin. Code cloning tracing: A "pay per trace" approach. In EuroPar'99 Parallel Processing, Toulouse, France, August 1999.
13. M. J. Litzkow, M. Livny, and M. W. Mutka. Condor - a hunter of idle workstations. In Proc. of the 8th Intl. Conf. on Distributed Computing Systems, pages 104-111, San Jose, Calif., June 1988.
14. M. Martonosi, A. Gupta, and T. Anderson. Effectiveness of trace sampling for performance debugging tools. In Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems, pages 248-259. ACM Press, 1993.
15. A. Nguyen, M. Michael, A. Nanda, K. Ekanadham, and P. Bose. Accuracy and speed-up of parallel trace-driven architectural simulation. In Proc. Int'l Parallel Processing Symp., IEEE Computer Soc. Press, pages 39-44, Geneva, Switzerland, April 1997.
16. D. B. Noonburg and J. P. Shen. A framework for statistical modeling of superscalar processor performance. In Proc. Thrird In. Symp. On High Perf. Computer Architecture, San Antonio, Texas, February 1997.
17. S. Nussbaum and J. Smith. Modeling superscalar processors via statistical simulation. In PACT '01, International Conference on Parallel Architectures and Compilation Techniques, Barcelona, September 2001.
18. D. Parello, O. Temam, and J.-M. Verdun. On increasing architecture awareness in program optimizations to bridge the gap between peak and sustained processor performance - matrix-multiply revisited. In Supercomputing 2002, Baltimore, November 2002.
19. V. Rajesh and R. Moona. Processor modeling for hardware software codesign. In International Conference on VLSI Design, Goa, India, January 1999.
20. T. Sherwood, E. Perelman, and B. Calder. Basic block distribution analysis to find periodic behavior and simulation points in applications. In International Conference on Parallel Architecture and Compilation Techniques, Barcelona, Spain, September 2001.
21. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In Proc. of Tenth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, Calif., October 2002.
22. Synopsys. SystemC. http://www.systemc.org, 2000-2002.
23. X. Vera, M. Hogskola, and J. Xue. Let's study whole-program cache behaviour analytically. In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, February 2002.
24. Z. Wang, K. Pierce, and S. McFarling. BMAT - a binary matching tool for stale profile propagation. Journal of Instruction-Level Parallelism, 2(1-6), 2000.